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characters to four rows of 40 characters. Graphic display versions of these modules are also available, allowing flexible text and graphic display formats.

Another method of driving small glass displays directly is through special LCD display driver chips, which are designed to drive a relatively simple display (such as one containing simple 7-segment numeric digits, for example). These peripherals are available from several vendors, and the LCD display peripheral driver hardware is even incorporated in some microcontrollers.

Many other types of I/O can be added externally using the processor’s bus interface. The 82C55 chip is a commonly used parallel interface with two 8-bit ports and two 4-bit ports which can be programmed as inputs or outputs. Connecting an 82C55 to the 8051 bus using memory mapping is an example of a program controlled I/O interface.

Program-Controlled I/O Bus Interfacing

In this form of I/O, the processor communicates with I/O devices in essen­ tially the same way it communicates with memory. The program running in the CPU must check the availability of data and transfer it, one piece at a time. The processor puts an I/O address on the bus, indicates the type of transfer, either read or write (I/O read or I/O write cycle for processors with an I/O address space). The CPU uses activates its control lines, and then transfers the data to or from the selected I/O device. The 8051 does not have an external I/O space, so these devices must be mapped into the external data memory address space. Processors with a separate I/O address space, such as the x86 family, have input and output instructions that cause the CPU to generate the appropriate I/O read and I/O write instructions respectively. Processors with a single address space, such as the 68000 family, have no I/O instructions. They use memory mapped I/O, so both software and hardware treat the I/O addresses in the same way as memory.

An I/O interface connects the actual I/O device, such as an LED, a switch or a printer, to the CPU. The job of the designer is to design an interface that meets the requirements of both the I/O device and the bus. While memory devices only read or write data, I/O devices may perform other operations as well. A typical I/O interface has several addresses, usually referred to as I/O ports or I/O registers, for different types of information such as data, commands, and

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register must be polled to determine if the device is ready. If the program is written to loop continuously waiting for the device to become ready, a lot of CPU time is wasted if the data is not available shortly after the polling begins. An example would be a keyboard, where keys are pressed at relatively slow and unpredictable rates. In order to minimize the time wasted in polling for these irregular data, interrupts are used. An interrupt is triggered by an event that is not synchronized to the main program and calls a special subroutine, referred to as an interrupt service routine (ISR that transfers the data. This “on-demand” processing is more efficient when data rates are relatively slow or unpredictable. At the other extreme however, when peak data transfer rates are high as they are in a disk drive, another technique that reduces the amount of work the CPU must do to transfer I/O data is used. The I/O interface trans­ fers data directly between the I/O device and memory without CPU interven­ tion using direct memory access (DMA).

Real-Time Processing

Some applications demand that the CPU respond to external events and pro­ cess them in a finite amount of time. Real-time processing means that data are processed at the same rate that they occur. They are event-driven which means they are triggered by external events, such as the tick of a clock, completion of I/O, etc. Examples of real-time PC programs are the flight control program on the Space Shuttle, arcade games, speech processing software, and flight simu­ lators. Examples of non-real-time PC programs would be word processors and accounting programs.

Direct Memory Access (DMA)

Direct memory access (DMA) requires that the I/O interface be active and semiintelligent, since it must count the words and increment the memory address for each element transferred in addition to performing the actual transfer.

The transfer process involved with DMA is typically as follows:

1)The program writes into the I/O control register of the interface:

a)The type of transfer (I or O).

b)The number of bytes or “block size” to transfer.

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Burst mode has low overhead and can handle the highest peak data rates, but the CPU can get locked out of memory for intervals that are as long as the longest block to be transferred. If the transfer is longer than the shortest inter­ rupt interval, such as the real time clock tick interval, interrupts can get lost.

Cycle Stealing

In this mode, DMA transfers are completed during bus cycles that are not used by the CPU, so no arbitration needs to be done. Most modern, high performance processors utilize almost 100% of available memory bandwidth however, so there isn’t much available for DMA. To save time, it is possible to perform arbitration and data transfer overlapping in time.

In general, burst mode DMA is more effective when relatively short time durations are needed to transfer the data block. Under those conditions, the bus is fully utilized for a short time interval. The DMA controller acquires access to the memory, transfers an entire block of data, and then releases the memory. An entire block of data is transferred in one short burst. The disad­ vantage is that a burst mode DMA device “hogs” the bus, thus preventing any other device from accessing memory during the burst. If the burst lasts too long, it may prevent the CPU from servicing certain time critical events, such as the real time clock interval (clock tick). In that case, the clock would run slower than it should because it would cause the CPU to miss some of the clock ticks. Therefore, burst mode DMA is most effective for data that is trans­ ferred at a high peak rate for short intervals. Typically, the data within a burst comes in too quickly to allow the arbitration handshaking required for the DMA controller to acquire and release the data between each data element. An example of this situation is the transmission or reception of data on a high-speed local area network interface. Small packets of data come across the network in high-speed (less than one microsecond per byte) bursts, with relatively low packet rates (milliseconds between packets).

For single cycle mode, the DMA controller acquires access to memory, transfers one word, and releases the memory. That allows other memory transfers to be interleaved with the DMA. That is why this mode is also referred to as “inter­ leaved DMA.” Single cycle DMA is better suited to transferring data over longer periods of time, where there is enough time to acquire and release the bus for every word transferred. In this case, the CPU and other devices can still access

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Hardware Design

the memory, at a reduced bandwidth. As a result, the CPU may be a bit slower because it will sometimes have to wait for a DMA cycle to complete, but it is not entirely shut out when a DMA transfer is in progress. When a single cycle DMA transfer occurs, more time is used in acquiring and transferring control of the memory to and from the DMA controller since it happens so much more fre­ quently. This “overhead” frequently reduces the overall available memory band­ width, especially when it is performed sequentially with the data transfers. Some systems overlap the memory bus arbitration handshaking with the memory data transfers so that the arbitration does not slow down the data transfers.

Direct memory access is required when the CPU is too slow to transfer the data under program control. Because the CPU does not have to participate directly in the item-by-item transfer of data, DMA is also useful when there are other tasks that the CPU can perform. In those cases, DMA transfers may be used even though they are not strictly required by the data rate.

Elementary I/O Devices and Applications

Parallel ports are the simplest form of I/O, but there are many different types of electrical interfaces ranging from the simple open collector TTL outputs used on a PC printer port to high-speed peripheral interfaces such as the IEEE-488 and SCSI buses. Most embedded controller ICs have some pins that are config­ urable as parallel input or output. These interfaces are appropriate for simple I/O, such as key switch and display interfacing. They are also appropriate for controlling and monitoring high-level interfaces such as solid-state relays.

The parallel I/O ports available on the 8051 family and similar processors are fairly versatile, with special internal circuitry to allow a port bit to be config­ ured individually as an input or output. Some microcontrollers also provide considerable current source and sink capability, however the 8051 family parts are usually fairly weak in that regard.

Serial ports, also referred to as asynchronous or synchronous communications (COM) interfaces, are commonly used to interconnect with devices, such as modems, which inherently transmit the data one bit at a time over a commu­ nication link such as a phone line. The RS-232 serial interface used in a PC’s COM port is an asynchronous serial data stream. An asynchronous interface

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has no explicit clock signal to synchronize the transfer of data. The timing of bits is based on the absolute bit rate, and is synchronized on every character with a start bit. The serial to parallel conversion is performed by a UART (universal asynchronous receiver-transmitter). When transmitting data, the UART appends a start bit before the data, shifts out the data LSB first, and adds a stop bit after the data. Once the transmission is complete, the UART sets a status bit indicating that the data has been sent and that it is ready to begin transmission of another character.

When receiving data, the UART looks for and synchronizes to the leading edge of a start bit. Then, it delays for one and one-half of a bit period, so that it samples the LSB in the middle of the bit period. Then, the UART delays one bit period, samples the next to the LSB, etc. until all the bits have been shifted in. Once all the data has been received, it is loaded into a buffer register and a status bit is set to indicate that the receive buffer contains a character and may be read by the CPU. In order for this method to work, the two UARTS at each end of the communication must have bit rate clocks that are accurate enough to guarantee that the data will be sampled at the right time. This typically requires a sample clock that is 16 times the data rate, accurate to 1% to 2%.

Timers and counters, which are present in most microcontroller chips, allow generation of pulses and interrupts at regular intervals. They can also be used to count pulses and measure event timing. Some of the more sophisticated versions can measure frequency, pulse width, and relative pulse timing on inputs. Outputs can be defined to have a given repetition rate, pulse width, and even complex sequences of pulses in some cases. In most cases, one of the timers can be used to generate the necessary serial clocks required to operate a microcontroller’s on-chip UART. In order to meet the approximately1% clock frequency accuracy for the 16x data rate clocks, the crystal frequency is often chosen to allow exact integer division of the crystal frequency resulting in an accurate, standard serial data rate. This is why 8051 family parts that use their internal counters and serial port to connect to standard 9600 bps and higher data rates use the crystal frequency 11.059 MHz rather than an even 12 MHz.

Analog to digital converters (ADCs) and digital to analog converters (DACs) are used to convert continuously variable real world parameters to digital form and back to analog. Examples include conversion of the output voltage of a temperature sensor into digital form for processing, and converting control