Файл: Embedded system development and labs for ARM (R. Muresan, 2005).pdf

Embedded Systems Development and Labs; The English Edition

After the software is burnt into the hardware, the users can use the hardware debugging function provided by Embest to debug or improve the software that is executed by the real hardware.

3.8.5 Operation Steps

1)Open the interwork project at the sample program directory (C:\EmbestIDE\Examples\Samsung\S3CEV40), and perform the following project settings:

(a) At the “Assembler” page, select “Make the assembled code as supporting interworking” shown in Figure 3-15.

(b) At the “Compiler” page, select “ARM interworking” shown in Figure 3-16.

(c) Click on the Thumb files, select the options shown in Figure 3-17 to Figure 3-19.

2)Refer to the former Labs, compile and link the interwork project files. Download and debug, single step execute program, analyze the result through the Memory/Register/Watch/Variable windows.

3)Use Embest IDE Disassemble all tool convert the elf file to objdump file. Open and watch the storage of the code, check the definition of the text section defined at linker script, compare it with the real source code, master the problem searching method through the objdump file and the source files.

Figure 3-15 Embest IDE Assembler Settings

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Figure 3-16 Embest IDE Compiler Settings

Figure 3-17 Select If Use Specific Compile Settings

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Figure 3-18 Select Setting the Output Format of the Target Code of C Programs

Figure 3-19 Select Setting the Output Format of the Target Code of Assembly Programs

4) Use elf2bin to convert the elf file into bin file. Compare the source code and objdump file in the IDE and get a better understanding of the linking location of the source code.

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5)Single step execute the ARM and Thumb mutual call disassembled programs, analyze the status changing process of ARM core.

6)After understanding and mastering the lab, finish the Lab exercises.

3.8.6 Sample Programs 1. arm.c

extern char arm[20]; static void delay(int time)

{

int i, j, k;

k = 0;

for(i=0; i<time; i++)

{

for(j=0; j<1000; j++) k++;

}

}

void arm_function(void)

{

int i;

char * p = "Hello from ARM world"; for(i=0; i<20; i++)

arm[i] = (*p++); delay(10);

}

2. entry.s

.equ count, 20

.global Thumb_function

.text

#.arm

mov r0, #count

mov r1, #0 mov r2, #0 mov r3, #0 mov r4, #0 mov r5, #0 mov r6, #0

loop0:

add r1, r1, #1

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add r2, r2, #1 add r3, r3, #1 add r4, r4, #1 add r5, r5, #1 add r6, r6, #1 subs r0, r0, #1 bne loop0

# thumb

.thumb Thumb_Entry:

mov r0, #count

mov r1, #0 mov r2, #0 mov r3, #0 mov r4, #0 mov r5, #0 mov r6, #0

loop1:

add r1, #1 add r2, #1 add r3, #1 add r4, #1 add r5, #1 add r6, #1 sub r0, #1 bne loop1

bl Thumb_function

.end

3. random.s

#Random number generator

#This uses a 33-bit feedback shift register to generate a pseudo-randomly

#ordered sequence of numbers which repeats in a cycle of length 2^33 - 1

#NOTE: randomseed should not be set to 0, otherwise a zero will be generated

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#continuously (not particularly random!).

#This is a good application of direct ARM assembler, because the 33-bit

#shift register can be implemented using RRX (which uses reg + carry).

#An ANSI C version would be less efficient as the compiler would not use RRX.

randomnumber:

#on exit:

#a1 = low 32-bits of pseudo-random number

#a2 = high bit (if you want to know it)

.GLOBAL seed

seed:

.LONG 0x55555555

.LONG 0x55555555

#END

4. thumb.c

extern void arm_function(void); char arm[22];

char thumb[22];

static void delay(int time)

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Embedded Systems Development and Labs; The English Edition

{

int i, j, k; k = 0;

for(i=0; i<time; i++)

{

for(j=0; j<1000; j++) k++;

}

}

int Thumb_function(void)

{

int i;

char * p = "Hello from Thumb World"; arm_function();

delay(10); for(i=0; i<22; i++)

thumb[i] = (*p++); while(1);

}

3.8.7 Exercises

(1)Read 44binit.s boot file, try to understand every line of this program.

(2)Write an assembly program and a C Language program to implement transferring parameters from a C mathematic function to an assembly mathematical function and return the result from the C function. Name the new project as “smath”. Add the 44init.s to the project. Refer to the project settings in the basic Labs. Use the ldscript linker script file in the “common” directory. After the compiling and linking, use the Embest tools to disassemble all and elf2bin to convert and analyze the output file. Connect the software emulator and download file at 0x0C000000 to start the debugging, tracing and program execution.

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Chapter 4 Basic Interface Labs

4.1 Memory Lab

4.4.1 Purpose

●Get familiar with the ARM memory space.

●Get familiar with configuring the memory space through registers.

●Learn how to access and view memory locations.

4.4.2 Lab Equipment

●Hardware: Embest S3CEV40 hardware platform, Embest Standard/Power Emulator, PC.

●Software: Embest IDE 2003, Windows 98/2000/NT/XP operation system.

4.1.3 Content of the Lab

Learn how to configure and read/write the S3C44B0X memory space. Use assembly and C language to read/write words, half-words, bytes, half bytes from/to RAM.

4.1.4 Principles of the Lab 1. Memory Controller

The S3C44B0X memory controller provides the necessary memory control signals for external memory access. S3C44B0X has the following features:

●Little/Big endian (selectable by an external pin)

●Address space: 32Mbytes per each bank (total 256MB: 8 banks)

●Programmable access size (8/16/32-bit) for all banks

●Total 8 memory banks. 6 memory banks for ROM, SRAM etc. 2 memory banks for ROM, SRAM, FP/EDO/SDRAM etc.

●7 fixed memory bank start address and programmable bank size

●1 flexible memory bank start address and programmable bank size

●Programmable access cycles for all memory banks

●External wait to extend the bus cycles

●Supports self-refresh mode in DRAM/SDRAM for power-down

●Supports asymmetrically or symmetrically addressable DRAM

Figure 4-1 shows the memory space of S3C44B0X (after reset). The special function registers are located at 4M-memory space from 0x01C00000 to 0x20000000. The start addresses and size of Bank0-Bank5 are fixed. The start address of Bank 6 is fixed, but its size is changeable. Bank 7 memory can be configured as 2/4/8/16/32 Mb and its start address and size are not fixed. The detailed relationship between the memory address and memory size of Bank 6 and Bank 7 memory is shown in Table 4-1.

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Note: SROM means ROM or SRAM

Figure 4-1 S3C44B0X Memory Space (after reset)

Table 4-1 Bank6/Bank7 Addresses

1) Big/Small Endian Selection

While nRESET is L, the ENDIAN pin defines which endian mode should be selected. If the ENDIAN pin is connected to Vss with a pull-down resistor, the little endian mode is selected. If the pin is connected to Vdd with a pull-up resistor, the big endian mode is selected. This is shown in Table 4-2.

2) Bank0 Bus Width

The data bus width of BANK0 (nGCS0) should be configured as one of 8-bit, 16-bit and 32-bit. Because the BANK0 is the booting ROM bank (mapped to 0x0000_0000), the bus width of BANK0 should be determined before the first ROM access, which will be determined by the logic level of OM[1:0] at Reset.

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Table 4-2 Big/Samll Endian

Table 4-3 Bus Width Selections

3) Memory Controller Specific Registers

Memory Controller Specific Registers includes Bus Width & Wait Control Register (BWSCON), Bank Control Register (BANKCONn: nGCS0-nGCS5), Refresh Control Register, Banksize Register, SDRAM Mode Register Set Register (MRSR) shown in Table 4-4 to Table 4-8.

The format of Bus Width & Wait Control Register (BWSCON) is shown in Figure 4-2.

Table 4-4 Bus Width & Wait Control Register (BWSCON)

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Figure 4-2 BWSCON Register Format Table 4-5 Bank Control Register (BANKCONn: nGCS0-nGCS5)

Table 4-6 Refresh Control Register

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Table 4-7 Banksize Register

Table 4-8 SDRAM Mode Register Set Register (MRSR)

For the detailed definition of the above registers, please refer to S3C44B0X specification.

The following is an example of the 14 memory control registers settings:

ldr r0, =SMRDATA /* loads r0 with the address SMRDATA */

ldmia r0, {r1-r13} /* loads registers r1 to r13 with the consecutive words stored at SMRDATA */

ldr r0, =0x01c80000 ; BWSCON Address

stmia r0, {r1-r13} SMRDATA DATA

DCD 0x22221210 ; BWSCON DCD 0x00000600 ; GCS0 DCD 0x00000700 ; GCS1 DCD 0x00000700 ; GCS2 DCD 0x00000700 ; GCS3 DCD 0x00000700 ; GCS4 DCD 0x00000700 ; GCS5

DCD 0x0001002a ; GCS6, EDO DRAM(Trcd=3, Tcas=2, Tcp=1, CAN=10bit) DCD 0x0001002a ; GCS7, EDO DRAM

DCD 0x00960000 + 953 ; Refresh(REFEN=1, TREFMD=0, Trp=3, Trc=5, Tchr=3) DCD 0x0 ; Bank Size, 32MB/32MB

DCD 0x20 ; MRSR 6(CL=2) DCD 0x20 ; MRSR 7(CL=2)

The 13 control registers are located at consequent memory addresses starting from 0x01C80000. As a result, the instruction “stmia r0, {r1-r13}” writes the configuration data to the corresponding registers. The Embest S3CEV40 memory (SROM/DRAM/SDRAM) address pin connection are shown in Table 4-9.

4) Memory (SROM/DRAM/SDRAM) Address Pin Connections

The Embest S3CEV40 chips select signals usage is shown in Table 4-10.

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Table 4-9 Memory (SROM/DRAM/SDRAM) Address Pin Connections

Table 4-10 chips select signal usage

5) Peripherals accesses address settings

The peripherals accesses address settings is shown in Table 4-11.

Table 4-11 Peripherals accesses address settings

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