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Embedded Systems Development and Labs; The English Edition

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5.3.8 Exercises

Refer to the LCD Display Lab and write a program that accepts 4 points pressed on the touch panel and display the rectangle using the 4 coordinate values.

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Chapter 6 Communication and Voice Interface Labs

6.1 IIC Serial Communication Lab

6.1.1 Purpose

●Understand the usage of IIC serial communication protocol.

●Learn the method of writing/reading the EPROM component of the board.

●Learn the usage of the S3C44BoX Micro IIC controller via the Lab.

6.1.2 Lab Equipment

● Hardware: Embest S3CEV40 hardware platform, Embest Standard/Power Emulator, PC. ● Software: Embest IDE 2003, Windows 98/2000/NT/XP operation system.

6.1.3 Content of the Lab

Write a program that can read and write the AT24C04 EPROM component on the development board. Implement a program that can write data to an address, read it from the same address and compare the results. Test the functionality of the EPROM AT24C04 and the microprocessor IIC interface.

6.1.4 Principles of the Lab

1. IIC Interface and EEPROM

IIC bus is a serial synchronized data transfer bus. Its standard data transfer rate is 100kb/s. The enhanced bus data transfer rate is 400kb/s. The IIC bus control can be organized as multi-master system or master-slave system. In multi-master system, the system gets the bus control via hardware arbitration or software arbitration. In applications, master-slave system is most often used. The master-slave system has only one main control point while other devices on the bus are all slaves. The addresses of the devices on the IIC bus are determined by the address bus interconnection. The lowest bit of the address determines the direction of read and write.

Currently most of the memory chips are EEPROM and their most often-used communication protocols are two wires serial interconnection protocol (IIC) and three wires serial interconnection protocol.

There are many models of IIC EPROM. The AT24CXX series are common used model. The AT24CXX series include AT2401/02/04/08/16, etc. They support 2-5V low voltage operation and their bit capability (bits/page) is 128x8 / 256x8 / 512x8 / 1024 x8/ 2048x8.

AT24Series chips are manufactured using the CMOS technology. With an internal high voltage charge pump, AT24Series chips can work from a single power supply. The standard package is 8-pin DIP package as shown in Figure 6-1.

Figure 6-1 Standard Package Pins

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The pin description is the following:

A2, A1, A0 A2, A1, A0 are input pins of the component/page address. The A2, A1 and A0 pins are device address inputs that are hard wired for the AT24C01A and the AT24C02.

WP: The AT24C01A/02/04/16 has a Write Protect pin that provides hardware data protection. The Write Protect pin allows normal read/write operations when connected to ground (GND). When the Write Protect pin is connected to VCC, the write protection feature is enabled.

VCC/GND: +5 V/0V power supply.

2. IIC Bus Read/Write Control Logic

●Start Condition Signal (START_C): A Start condition can be initiated with a High-to-Low transition of the SDA line while the clock signal of SCL is High.

●Stop Condition Signal (STOP_C): A stop condition is a Low-to-High transition of the SDA line while SCL is High.

●ACK Signal (ACK): In Stop Condition, ACK will make the SDA line low when a word was received.

●READ-WRITE Signal (READ-WRITE): After the IIC bus started and got an acknowledgment, the serial data will be transferred when SCL is high; the data will be ready when SCL is low. The data will be transferred in 8-bit unit that begin with MSB bit. The time sequence diagram is shown is Figure 6-2.

Figure 6-2 IIC Time Sequence Diagram

3. EEPROM Read/Write Operation

1) AT24C04 Architecture and Application

AT24C04 consists of an input buffer and an EEPROM array. Because the write time is 5-10ms, if data is written to the EPROM directly from the data bus, there will be a 5-10ms wait time for every byte that needs to be written in. To speedup the writing operation the EEPROM has an input buffer. In this case, the write operation is actually a write operation to the buffer. After the data is loaded into the buffer, an automatic writing logic will be

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launched to write all the data from the buffer into the EPROM array. Writing to buffer is called page writing. The capability of the buffer is called ‘page write byte’. The page write byte of AT24C04 is 8. It occupies the lowest three bits of the address line. When the amount of data is not exceeding the page write byte, the write operation to EPROM is the same as the write operation to SRAM. When the amount of data is exceeding the page write byte, another write operation to EPROM will be initiated after a 5-10ms wait time.

2) Device Address (DADDR)

The AT24C04 device address is 1010.

3) AT24CXX Data Operation Format

In order to write or read the EPROM memory, both the device address (DADDR) and the read/write page address (PADDR) should be given. These two addresses form the operation address (OPADDR) as following: 1010 A2 A1 –R/W

In the Embest ARM Development system, pins A2A1A0 are 000 and the system can access all pages of the AT24C04 (4k). The format of the read/write data operation to an address (ADDR=1010 A2 A1 –R/W) is as following:

(1) Write Format

The time sequence diagram for writing one byte to the address ADDR_W is shown in Figure 6-3. The write format is:

START_C OPADDR_W ACK ADDR_W ACK data ACK STOP_C

Figure 6-3 Write One Byte

The time sequence diagram for writing n bytes to the address ADDR_W is shown in Figure 6-4. The write format is:

START_C OPADDR_W ACK ADDR_W ACK data1 ACK data1 ACK … datan ACK STOP_C

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Figure 6-4 Writing N Bytes

(2) Read Format

The time sequence diagram for reading n bytes from the address ADDR_W is shown in Figure 6-5. The read format is:

START_C OPADDR_R ACK ADDR_R ACK OPADDR_R ACK data STOP_C

Figure 6-5 Read One Byte

The time sequence diagram for reading 1 byte from the address ADDR_W from the same page is shown in Figure 6-6. The read format is:

START_C OPADDR_R ACK ADDR_R ACK OPADDR_R ACK data STOP_C

Figure 6-6 Read N Bytes

In reading 1 bytes operation, besides the read address ADDR_R, the operation address OPADD_R is also needed. As a result, before the 1 byte of data is read, a one byte writing operation is needed. Notice that there is no ACK after the read operation.

4. S3C44B0X Processor IIC Interface

1) An introduction to the S3C44BOX IIC interface

The S3C44B0X RISC microprocessor can support a multi-master IIC-bus serial interface. There are dedicated

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serial data line (SDA) and a serial clock line (SCL) carry information between bus masters and peripheral devices that are connected to the IIC-bus. The SDA and SCL lines are bi-directional. A High-to-Low transition on SDA can initiate a Start condition. A Low-to-High transition on SDA can initiate a Stop condition while SCL remains steady at High Level. The S3C44B0X IIC-bus interface has four operation modes:

—Master transmitter mode

—Master receiver mode

—Slave transmitter mode

—Slave receiver mode

In the Master Transmitter Mode, the microprocessor communicates to the serial devices via IIC bus using the following registers:

(1) MULTI-MASTER IIC-BUS CONTROL REGISTER (IICCON)

(2) MULTI-MASTER IIC-BUS CONTROL/STATUS REGISTER (IICSTAT)

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3) MULTI-MASTER IIC-BUS ADDRESS REGISTER (IICADD)

4) MULTI-MASTER IIC-BUS TRANSMIT/RECEIVE DATA SHIFT REGISTER (IICDS)

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The IIC-Bus Controler Block Diagram is as following:

Figure 6-7 IIC-Bus Controller Block Diagram

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6.1.5 Lab Design

1. Program Design

The flow diagram of IIC program is shown is Figure 6-8.

Start

End

Figure 6-8 IIC Program Flow Diagram

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2. Circuit Design

In the Embest S3CEV40, the S3C44B0X on-chip IIC controller is the master and the AT24C04 EEPROM is the slave. The circuit design is shown in Figure 6-9.

GND

Figure 6-9 AT24C04 EEPROM Control Diagram

6.1.6 Operational Steps

(1)Prepare the Lab environment. Connect the Embest Emulator to the target board. Connect the target board UART0 to the PC serial port using the serial cable provided by the Embest development system.

(2)Run the PC Hyper Terminal (set to 115200 bits per second, 8 data bits, none parity, 1 stop bits, none flow control).

(3)Connect the Embest Emulator to the target board. Open the IIC_Test.ews project file found in the IIC_Test sub directory in the Example directory. After compiling and linking, connect to the target board and download the program.

(4)Watch the hyper terminal. The sample program write/read data to/from the same address and compare the results. If write/read is successful, the following will be displayed:

Embest 44B0X Evaluation Board (S3CEV40) IIC operation test example

IIC test using AT24C04… Write char 0-f into AT24C04 Read 16 bytes from AT24C04

(5) After understanding and mastering the lab, finish the Lab exercises.

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