Файл: Introduction to microcontrollers (G. Gridling, 2006).pdf

Ideally, all s samples of the start bit should be zero. However, to be more resilient to noise, the UART only uses some of the samples to determine the value of the bit. The ATmega16, for example, has s = 16 and uses samples 8, 9, 10 and a majority vote to determine the state of the line. If two or more of the samples are high, the start bit is discarded as a spike on the line, otherwise it is recognized as the beginning of a transmission.

All subsequent bits of a packet are again sampled s times and the same technique as for the start bit is used to determine the bit value. The data bits are put into a receive shift register and are generally copied into a buffer register at the end of reception. The buffer register frees the shift register for the next data reception even if the application has not yet read the last data. The transmission is concluded with the stop bit(s).

There are some errors that may occur here: First of all, there may have been bit errors due to noise on the wire. If the packet included a parity bit, single bit errors (or more generally an odd number of bit errors) can be detected and are announced to the user. The data bits are still copied into the buffer register, but a parity error bit is set in the UART status register to indicate that there was a parity violation.

Secondly, it may occur that the baud rates of sender and receiver diverge too much, so that the receiver gradually lost synchronization during the transmission. This may be recognizable at the stop bit, where the UART expects to read a high level. If the stop bit was not recognized, a frame error is announced to the application. But of course there may be situations, e.g. when the receive clock is slow, where the idle state of the line is mistaken as the stop bit and the error is not recognized.

Finally, even though the UART generally uses a buffer register to give the application more time to read incoming data, so that a second transmission may begin before the data from the first was processed, it may occur that a third transmission is started before the data from the first message was read. In such a case, a data overrun occurs and the data in the shift register is lost. Such a data overrun is again indicated by a flag in the UART’s status register.

Baud Rate Generation

The baud rate is derived from the system clock by means of a counter. A baud rate register, which basically serves the same function as the output compare register described in Section 2.6.3, is used to generate a periodic clock signal. This signal is then scaled down (by s) to the desired baud rate using a prescaler. At the receiver, the same mechanism is used, but the clock signal is taken from before the prescaler. So the receiver samples s times faster than the bit rate. Since the sampling rate is generated from the receiver’s system clock, only signals with a bit rate of ≤ 1/s-th of the receiver clock rate can be handled.

As a side-effect of generating the baud rate from the system clock, the set of baud rates offered by a controller depends on its clock frequency. Furthermore, not every arbitrary baud rate can be achieved exactly. For example, if we have an 8 MHz clock and use oversampling with s = 8, we can get a baud rate of 0.5 Mbps exactly. A baud rate of 115.2 kbps, on the other hand, cannot be generated by the controller’s system clock, since we would have to scale down the maximum achievable baud rate by (8 MHz/s)/115.2 kHz = 8.68. We can only set our counter to integer values, so any baud rate that has a fractional part here cannot be generated exactly. Figure 3.4 shows the consequence of a slower than expected transmitter baud rate on the receiver.

The example uses s = 6, with a frame format of 3E1. Samples 3, 4, and 5 are used for voting. The top half shows the transmitter view, the bottom half the receiver view. As you can see, the receiver

receive clock (bit rate)

Figure 3.4: Baud rate of sender is too slow, receiver loses synchronization (3E1, s = 6).

synchronizes itself to the start bit and then gradually loses synchronization because it is faster than the transmit clock. Nevertheless, the data bits are still recognized correctly, even though the samples are not in the center of the transmitted bits, but move closer towards the left edge with every bit. Since the sampling algorithm uses a voting algorithm to determine the bit value, even the parity bit is still recognized correctly, even though the first of its samples has in fact read the value of data bit D2. Only at the stop bit does the receiver realize that something is amiss.

Still, had the sender been just a bit faster, or had we used a 2E1 data format, the receiver would have recognized the stop bit as well (even though perhaps inexactly, like the parity bit in our example). So apparently an exact match of sender and receiver clock is not necessary, as long as we keep the frequencies close enough together. It is also obvious that the longer the frame, the closer together the frequencies have to be, because the receiver must still be close enough at the stop bit to detect it correctly.

So if we come back to our example of B = 115.2 kbps with an f = 8 MHz clock and s = 8, we could set our counter to C = 9 because this is closest to the 8.68 we require4. The resulting baud rate

so in our case we would get an error of -3.5% . To determine whether this is acceptable for our frame format, we have to compute how much the receive clock will diverge from the send clock during transmission. If the majority of samples taken for one bit fall into the stop bit, the transmission will be successful. If the majority of samples is outside, synchronization will be lost.

Let us assume that the sender operates with sampling frequency ft (so the bit rate is ft/s)5 and the receiver samples with frequency fr. From the s samples s0, · · · , ss−1 taken by the receiver, samples

4Note that e.g. on the ATmega16, this implies that the baud rate register has to be set to 8, because the counter starts at 8 and counts down to including zero, scaling the timer down to 1/9-th of its frequency.

5To simplify our computations, we use the sampling frequency and not the system clock frequency of the device here. If the system clock frequency is f, you get the sampling frequency by dividing through the counter value C.

If ft and fr are given, then an upper bound on the frame length k might be of interest. Here, it is useful to note that the left inequality of Equ. (3.3) is important for fr > ft. In that case, the worst case is that o = 0. For fr ≤ ft, the left inequality is always true. Similarily, the right part is only important for fr < ft and always true otherwise. Here, the worst case is that o = 1/fr. So assuming given fr and ft, we get the conditions

For fr = ft we have perfect synchronization and k = ∞.

Note that the above bounds are only valid under the assumption that there is no noise on the line. If spikes can occur, then some of the samples taken could have a wrong value. To tolerate e such erroneous samples, not only sample svn but samples svn−e, . . . , svn+e have to be taken from bit k and the upper and lower bounds of the previous equations have to be adapted accordingly.

RS-232

The UART itself is only the implementation of the asynchronous serial communication protocol but does not define any physical characteristics of the interface, like the voltage levels used. In the microcontroller, the bits are just mapped to the controller’s voltages for 0 and 1. With a suitable voltage translation device, however, a UART can be used with a wide range of physical interfaces. The most common one is the RS-232 standard which can be found in PCs.

The RS-232 is a single-ended serial connection intended for point-to-point communication. It defines communication equipment types, electrical specifications, signal lines and signal timing. The RS-232 standard provides for 25 lines (you probably know the 25-pin serial connectors), although PCs generally only use 9 of these lines (the well-known D-SUB9 connectors). Of these nine bits, only two (RXD and TXD) are used by the UART. A third (GND) is required because the connection is single-ended. The rest are control lines that can be used with more advanced communication protocols.

The RS-232 specification defines the signal voltage levels to be within ±3-15V, and devices must be able to withstand a maximum of ±25V. Control lines use positive logic, data lines use negative logic.

Since the microcontroller is not capable of handling the voltages required by the RS-232 interface, a conversion IC has to be used that translates the GND and VCC levels of the controller to the voltage levels used by the RS-232 and vice versa. In our lab, for example, we use a MAX232 for this purpose. The chip uses an internal charge pump to generate ±12V from a 5V supply voltage.

RS-422

The RS-422 standard is also designed for point-to-point communication, just like the RS-232. However, it uses differential lines (both RXD and TXD consist of twisted-pair wires) for transmission. Hence, it does not need a common GND wire. The RS-422 can be used instead of the RS-232 to extend the transmission range of the UART. It is also the better choice in noisy environments.

USART

The Universal Synchronous Asynchronous Receiver Transmitter (USART) extends the functionality of the UART by a synchronous transmission module. The USART therefore has an additional third line which carries a clock signal. In synchronous mode, the clock signal is generated by one of the communication partners and is used by both for data transmission and reception. Naturally, this synchronous communication makes the oversampling mechanism of the asynchronous module unnecessary, so the synchronous mode is by a factor s faster than the asychronous mode. The USART module combines the logic for both synchronous and asynchronous communication. If asynchronous communication is used, the clock line is free and can generally be used as a normal digital I/O pin.

3.2 SPI

The Serial Peripheral Interface (SPI)7 is a simple synchronous point-to-point interface based on a master-slave principle. It provides full-duplex communication between a master (generally a controller) and one (or more) slaves (generally peripheral devices). The interface consists of four lines:

MOSI (Master Out, Slave In): This line is used by the master to transmit data to the slave.

MISO (Master In, Slave Out): This line is used by the slave to transmit data to the master.

SCK (System Clock): This line is used by the master to transmit the clock signal.

SS (Slave Select): This line is used by the master to select a slave.

Figure 3.6 shows the basic principle of the SPI interface. Both the master and the slave have an internal shift register which is operated by SCK. At each clock pulse, the msb (or lsb, this is generally configurable) of the master’s SPI register is shifted out on the MOSI line and shifted into the slave’s SPI register as lsb. At the same time, the slave’s msb is transmitted over the MISO line into the master’s register as lsb. After 8 such clock cycles, master and slave have exchanged all eight bits in their registers.

Figure 3.6: SPI interface.

The master must explicitly address the slave by setting SS to low. Hence, we can connect two slaves to the SPI if we let one of them react to SS directly, whereas the other first negates the line. By setting SS to low resp. high, the master can then select the first resp. the second slave.

If the master is prepared to use up more of its I/O pins, then the number of slaves can be extended to 2n for n addressing lines with the help of an external decoder.

7The SPI is also often used for programming a microcontroller and is therefore sometimes (erroneously) called Serial Programming Interface.