Файл: Introduction to microcontrollers (G. Gridling, 2006).pdf
ВУЗ: Не указан
Категория: Не указан
Дисциплина: Не указана
Добавлен: 14.06.2025
Просмотров: 1074
Скачиваний: 2
3.3. IIC (I2C) |
83 |
3.3 IIC (I2C)
The Inter-IC bus (IIC) is a synchronous bus that operates on a master-slave principle. It uses two wires SCL (Serial Clock Line) and SDA (Serial Data Line) for half-duplex communication. The protocol has been developed by Philips [Phi00] and is widely used for (short distance) communication between one or more controllers and peripheral devices.
The protocol specification distinguishes three speed modes: The standard mode encompasses transmission speeds up to 100 kbit/s, the fast mode extends this range to 400 kbit/s, and the highspeed mode increases the transmission rate to 3.4 Mbit/s. Due to the protocol’s properties, fast and high-speed devices can be mixed with devices of lower speed.
The protocol includes bus arbitration mechanisms and thus allows the co-existence of several masters. The role of master normally falls to the microcontroller, with all peripheral devices as simple slaves. In a system with several microcontrollers, you may choose for each controller whether it should be a master or a slave. The only condition is that there must be at least one master in the system.
One of the main advantages of the IIC bus is its easy extensibility. New devices can be added to the bus by just connecting them, see Figure 3.7. There is no specific limit on the number of devices connected to the bus as long as the maximum bus capacitance of 400 pF is not exceeded.
VDD |
I/O |
||
MCU |
RTC |
AD/DA |
LCD |
SDA |
|||
SCL |
Figure 3.7: Basic configuration of the IIC bus.
The IIC bus supports both 7-bit and 10-bit addresses. In 7-bit addressing all devices on the bus are identified by a 7-bit address, part of which (e.g. the highest 4 bit) are hard-coded by the manufacturer. The remaining bits can be programmed by the board designer. The addresses (0000XXX)2 and (1111XXX)2 are reserved, leaving 112 potential device addresses. To increase the number of addressable devices, the protocol was later extended to 10-bit addresses. Care was taken, however, to remain compatible to the original 7-bit addressing mode, so 7-bit address devices can still be used in the new addressing scheme. In this section, we will focus on the 7-bit addressing scheme. Details to 10-bit addressing can be found in the specification [Phi00].
We have not explicitly mentioned it until now, but it is obvious that the peripheral devices must already include an IIC (slave) interface to make the “plug-and-play” feature of Figure 3.7 possible. Manufacturers who wish to equip their devices with an IIC bus interface need to obtain a licence from Philips and can then incorporate the protocol into their devices. Likewise, microcontrollers sometimes
84 |
CHAPTER 3. COMMUNICATION INTERFACES |
already have an integrated IIC module that implements the protocol8. As do other interface modules, it provides the programmer with high-level access functions. It also allows the programmer to select between master and slave mode and to define the communication parameters like transmission speed or receiver address.
3.3.1Data Transmission
The IIC is a single-ended bus, voltage levels are defined with respect to a common ground. The low level input voltage is in the range of -0.5 to 0.3VDD Volt, the high level input voltage is within 0.7VDD to VDD+0.5 V. A low level on the data line corresponds to a logical 0, a high level corresponds to logical 1.
Since the wires are connected to external pull-up resistors (in the range of about 1-10 kΩ), the high level is never driven. Instead, the sender simply tri-states its output and lets the wire be pulled up externally. Note that the protocol depends on this behavior, so if you want to program the protocol manually (a procedure also called bit-banging), you must not drive the high level. If you have to output a logical 1, set the controller pin to input instead. The low level is driven as usual, so just write 0 to the output pin.
This asymmetry between high and low level results in the line having a dominant and a recessive state: If a device outputs 0 and thus drives the line low, it remains low even if one or more devices output 1 (i.e., tri-state their output). Hence, a 0 always wins over a 1 (low is dominant, high is recessive). This behavior is often called wired-AND (because all senders have to output 1 for the line to be 1) and sometimes wired-NOR (probably because from the point of view of an open-collector output, if one device turns on its output transistor, then the bus goes low). As we will see later, the protocol exploits this property for speed control and bus arbitration.
The general layout of an IIC packet is depicted in Figure 3.8.
S
A6
...
A0 R/W ACK D7
...
D0 ACK D7
...
D0 ACK P/Sr
Figure 3.8: An IIC frame.
In their idle states, both SCL and SDA are high. The transmission is initiated by the master, who puts out a clock signal on SCL and generates a start condition (S) on SDA. Then, the master puts the address on the bus and states whether this is a read access (that is, the addressed device should transfer data) or a write access (the master transfers data to the device). After the R/W bit, the slave sends an acknowledge to indicate that it has recognized its address. Depending on the data direction, either the master or the slave can now transmit an arbitrary number of data bytes. Each byte is acknowledged by the receiver (with the exception of the last byte if the master is the receiver). At the end of the transmission, the master either generates a STOP condition (P) to indicate that the bus is now free, or it can keep the bus by sending a repeated START condition (Sr), which ends the current transmission and at the same time starts a new one.
8Note that Atmel calls its IIC module Two-wire Interface (TWI).
3.3. IIC (I2C) |
85 |
Start and Repeated Start
The START condition (S) is shown in Figure 3.9. It is characterized by a falling edge on the SDA line during a high level of the SCL line. Note that only the START and STOP conditions change the level of SDA during a high state of SCL. All normal data transmission including acknowledgements change the level during the low state of SCL.
SDA
SCL S
START condition
Figure 3.9: START condition (S).
The repeated START condition (Sr) is the same as the normal START condition. It replaces a STOP/START condition pair and is sent instead if the master intends to immediately use the bus again. In a single-master system, the Sr simply saves one clock cycle. In multi-master systems, the Sr prevents an arbitration phase (see Section 3.3.3) and thus ensures that the currently transmitting master keeps the bus.
Address
The 7-bit address is sent msb first. As with all normal data bits, the SDA level is changed during the low phase of SCL and is read during the high phase.
Direction Control
After the seven address bits, the master completes the byte with an eight bit (R/W) that indicates the direction of the subsequent transmission. If R/W is high, then the master wants to read data from the addressed slave. If the bit is low, the master intends to send data to the slave.
Note that every transmission on the bus is initiated by the master, who sends the slave address. If R/W is high, the slave sends its acknowledge. After that, data direction changes and the slaves starts transmitting data.
Acknowledgement
After every 8 bits, the receiver sends an acknowledge (ACK) to indicate that it has received the data. The ACK is achieved by setting SDA to low. The only exception is the final acknowledge of the master if it is the receiver: In that case, the master does not acknowledge the last byte, that is, SDA remains high. The high indicates to the transmitting slave that the end of the transmission has been reached. The slave then releases the data line to allow the master to transmit the repeated start or stop condition.
86 |
CHAPTER 3. COMMUNICATION INTERFACES |
Data
The data bits are transmitted like all other bits, and each byte must be acknowledged by the receiver. Data is transfered msb first. There is no limit on the number of data bytes that can be transmitted in one frame.
Stop
Figure 3.10 depicts the STOP condition (P). It mirrors the START condition, so SDA now goes from low to high while SCL is high.
SDA
SCL P
STOP condition
Figure 3.10: STOP condition (P).
The STOP condition (P) is transmitted by the master if it wants to give up the bus. As soon as the STOP condition has been sent, the bus is idle and can be requested by any master, see Section 3.3.3.
3.3.2Speed Control Through Slave
Since there is no way to negotiate the transmission speed between master and slave, the master simply transmits data with a fixed speed. Of course, the speed is matched to the specifications of the slave devices, but still it could occur that e.g. the slave needs some time to process data sent by the master. Hence, we need a means to tell the master to hold on for a while. The IIC protocol rather cleverly exploits the dominant/recessive nature of the clock line to provide speed control by the slave. Let us first define two phases of a clock signal: the low phase is the period during which the clock signal is low. Similarly, the high phase is the period during which the clock signal is high. To generate the signal, the master has to start the phase by an appropriate signal edge (rising or falling) and then wait until it is time to generate the next edge, just like a PWM signal is generated by the timer. Now to get speed control by the slave, the master does not generate its clock signal blindly, but reads back SCL and only starts timing the low resp. high phase after it has recognized a falling resp. rising edge on SCL. As a result, whenever the slave needs more time, it can simply set the clock line low. Since low is the dominant state, this will prolong the low time of the current clock tick and thus delay the master until the slave releases SCL. Since the master waits until the rising edge before timing the high phase, all subsequent clock cycles are just delayed but not affected.
This mechanism entails that IIC devices are pretty flexible as far as bit rate is concerned. Hence, the three speed modes provide maximum ratings, but the actual transmission speed on the bus can be arbitrarily low as long as the IIC bus timing constraints (which do not specify the duration of the clock cycles, but mostly deal with dependencies between the SDA and SCL lines) are met.
3.4. EXERCISES |
87 |
If you are implementing this in a bit-banging solution, do not forget that after setting SCL to high (by setting the pin to input), you must wait for the rising edge on SCL before you can start the timer that will set SCL to low again.
3.3.3Multi-Master Mode
For a multi-master system to work, we need some means to control bus access and to synchronize the multiple clock signals. The IIC bus specification utilizes the wired-AND property of the SDA and SCL lines to achieve these goals.
Let us look at SCL first: Assume that initially, each master generates its clock signal independently of the other masters and puts it on SCL. Due to the wired-AND property, the first master to generate a falling edge will set SCL to low. Since the masters read back the actual value of SCL, as described in Section 3.3.2, and start timing a low or high phase only after the corresponding edge has been detected on SCL, the first falling edge on SCL triggers timing of the low phase on all masters. Now one by one, the masters will finish their low phases and try to set SCL to high. However, as long as one master still remains low, the SCL line stays low due to the wired-AND property. Hence, the master with the longest low phase generates the low phase of the resulting SCL signal. When this master goes high, the SCL signal rises to high and all masters start timing their high phases. Here, the first master to finish its high phase will set SCL to low again, effectively ending the SCL high phase. Hence, the master with the shortest high phase generates the high phase of the resulting SCL signal.
Bus arbitration uses the wired-AND property of the SDA line. When the bus is idle, any master can generate the start condition and begin to transmit the slave address. Like with the SCL line, the master reads back the SDA line to check whether the bit it has written has actually made it to SDA. Again, a low level will be dominant, so a master who writes a 1 and reads back a 0 recognizes that another master is using the bus as well and stops transmitting. In the end, only one master will remain (except if two masters have sent exactly the same message, in which case backing off is not necessary).
3.3.4Extended Addresses
As we have already mentioned, the original 7-bit addressing scheme was later extended to 10-bit addresses. To allow compatibility with the original 7-bit addressing, one of the reserved 7-bit addresses (11110XX)2 was used to implement 10-bit addressing:
To write to a slave, the master sends (11110XX)2 in the address field and sets R/W to 0. The XX in the field are the two most significant bits of the 10-bit slave address. Each slave compares these two bits to the msb’s of its own address and acknowledges if there is a match. The master now sends the remaining 8 bits of the address in the next byte. Only one of the previously addressed slaves will find a match and acknowledge. After that, the master transmits data to the slave.
To read from a slave, the master first sends (11110XX)2 and sets R/W to 0. It then sends the low byte of the address and waits again for the acknowledge. After the acknowledge, the master generates a repeated start condition and again sends (11110XX)2, but this time sets R/W to 1. The slave that was addressed last will react to the match of the two msb’s and will start transmitting in the next byte.
3.4 Exercises
Exercise 3.1 Explain the differences between synchronous and asynchronous communication. Can
88 |
CHAPTER 3. COMMUNICATION INTERFACES |
you come up with a protocol that has both synchronous and asynchronous properties?
Exercise 3.2 Assume you have a UART frame format of 8E1. What percentage of the bandwidth is used for data, what is used up by the frame itself?
Exercise 3.3 Adapt equations (3.3)-(3.6) to account for e erroneous samples per bit. Remember: svn−e and svn+e now both have to be within bit k. How can you use your new formulas to account for an even s?
Exercise 3.4 You use the SPI to communicate with a peripheral device. What percentage of the bandwidth is used for data, what is used up by the communication frame itself?
Exercise 3.5 You use the IIC bus to transmit one byte of data to a slave. What percentage of the bandwidth is used for data, what is used up by the communication frame itself?
Exercise 3.6 We explained how the IIC bus synchronizes the clock signals of multiple slaves. How problematic is it that the resulting clock signal inherits the shortest high phase?
Exercise 3.7 How does the 10-bit addressing feature of the IIC bus affect 7-bit address devices?