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Introduction to Verilog
4.5. Integer
Integers are general-purpose variables. For synthesois they are used mainly loops-indicies, parameters, and constants. See“Parameter” on p. 5. They are of implicitly of type reg. However they store data as signed numbers whereas explicitly declared reg types store them as unsigned. If they hold numbers which are not defined at compile time, their size will default to 32-bits. If they hold constants, the synthesizer adjusts them to the minimum width needed at compilation.
Syntax |
Example 4 .4 |
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integer integer_variable_list; |
integer a; |
// single 32-bit integer |
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assign b=63; |
// 63 defaults to a 7-bit variable. |
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... integer_constant ... ; |
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4.6. Supply0, Supply1
Supply0 and supply1 define wires tied to logic 0 (ground) and logic 1 (power), respectively.
Syntax |
Example 4 .5 |
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supply0 logic_0_wires; |
supply0 my_gnd; // equivalent to a wire assigned 0 |
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supply1 logic_1_wires; |
supply1 a, b; |
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4.7. Time
Time is a 64-bit quantity that can be used in conjunction with the $time system task to hold simulation time. Time is not supported for synthesis and hence is used only for simulation purposes.
Syntax |
Example 4 .6 |
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time time_variable_list; |
time c; |
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c = $time; |
// c = current simulation time |
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4.8. Parameter
A parameter defines a constant that can be set when you instantiate a module. This allows customization of a module during instantiation. See also “Parameterized Modules” on page 11.
Syntax
parameter par_1 = value, par_2 = value, .....;
parameter [range] parm_3 = value
Example 4 .7
parameter add = 2’b00, sub = 3’b111; parameter n = 4;
parameter n = 4;
parameter [3:0] param2 = 4’b1010;
. . .
reg [n-1:0] harry; /* A 4-bit register whose length is set by parameter n above. */
always @(x)
y = {{(add - sub){x}}; // The replication operator Sect. 5.8. if (x) begin
state = param2[1]; else state = param2[2]; end
Friday, January 05, 2001 9:34 pm |
5 |
Peter M. Nyasulu |
Introduction to Verilog
5. Operators
5.1. Arithmetic Operators
These perform arithmetic operations. The + and - can be used as either unary (-z) or binary (x-y) operators.
Operators
+(addition)
-(subtraction)
*(multiplication)
/ (division) % (modulus)
Example 5 .1 |
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parameter n = 4; |
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reg[3:0] a, c, f, g, count; |
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f = a + c; |
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g = c - n; |
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count = (count +1)%16; |
//Can count 0 thru 15. |
5.2. Relational Operators
Relational operators compare two operands and return a single bit 1or 0. These operators synthesize into comparators. Wire and reg variables are positive Thus (-3’b001) = = 3’b111 and (-3d001)>3d110. However for integers -1< 6.
Operators
<(less than)
<= (less than or equal to)
>(greater than)
>= |
(greater than or equal to) |
== |
(equal to) |
!= |
(not equal to) |
Example 5 .2 |
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if (x = = y) |
e = 1; |
else |
e = 0; |
//Compare in 2’s compliment; a>b reg [3:0] a,b;
if (a[3]= = b[3]) |
a[2:0] > b[2:0]; |
else |
b[3]; |
Equivalent Statement
e = (x == y);
5.3. Bit-wise Operators
Bit-wise operators do a bit-by-bit comparison between two operands. However see“Reduction Operators” on p. 7.
Operators
~ (bitwise NOT)
&(bitwise AND)
| |
(bitwise OR) |
^ |
(bitwise XOR) |
~^ or ^~(bitwise XNOR)
Example 5 .3
module and2 (a, b, c); input [1:0] a, b; output [1:0] c; assign c = a & b;
endmodule
a |
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a(0 |
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2 |
b(0) |
c(0 |
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a(1) |
c(1) |
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b |
b(1) |
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2
5.4. Logical Operators
Logical operators return a single bit 1 or 0. They are the same as bit-wise operators only for single bit operands. They can work on expressions, integers or groups of bits, and treat all values that are nonzero as “1”. Logical operators are typically used in conditional (if ... else) statements since they work with expressions.
Operators
! (logical NOT) && (logical AND)
||(logical OR)
Example 5 .4 |
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wire[7:0] x, y, z; |
// x, y and z are multibit variables. |
reg a; |
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. . . |
if ((x == y) && (z)) a = 1; // a = 1 if x equals y, and z is nonzero. else a = !x; // a =0 if x is anything but zero.
Friday, January 05, 2001 9:34 pm |
6 |
Peter M. Nyasulu |
Introduction to Verilog
5.5. Reduction Operators
Reduction operators operate on all the bits of an operand vector and return a single-bit value. These are the unary (one argument) form of the bit-wise operators above.
Operators
&(reduction AND)
| |
(reduction OR) |
~& |
(reduction NAND) |
~| |
(reduction NOR) |
^ |
(reduction XOR) |
~^ or ^~(reduction XNOR)
Example 5 .5
module chk_zero (a, z);
input [2:0] a; |
a |
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output z; |
3 |
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assign z = ~| a; // Reduction NOR endmodule
a(0)
a(1) |
z |
a(2)
5.6. Shift Operators
Shift operators shift the first operand by the number of bits specified by the second operand. Vacated positions are filled with zeros for both left and right shifts (There is no sign extension).
Operators |
Example 5 .6 |
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<< |
(shift left) |
assign c = a << 2; |
/* c = a shifted left 2 bits; |
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vacant positions are filled with 0’s */ |
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>> |
(shift right) |
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5.7. Concatenation Operator
The concatenation operator combines two or more operands to form a larger vector.
Operators
{ }(concatenation)
Example 5 .7 |
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wire [1:0] a, b; |
wire [2:0] x; |
wire [3;0] y, Z; |
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assign x = {1’b0, a}; // x[2]=0, |
x[1]=a[1], |
x[0]=a[0] |
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assign y = {a, b}; |
/* y[3]=a[1], |
y[2]=a[0], |
y[1]=b[1], |
y[0]=b[0] */ |
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assign {cout, y} = x + Z; // Concatenation of a result
5.8. Replication Operator
The replication operator makes multiple copies of an item.
Operators
{n{item}} (n fold replication of an item)
Example 5 .8 |
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wire [1:0] a, b; wire [4:0] x; |
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assign x = {2{1’b0}, a}; |
// Equivalent to |
x = {0,0,a } |
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assign y = {2{a}, 3{b}}; |
//Equivalent to |
y = {a,a,b,b} |
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For synthesis, Synopsis did not like a zero replication. For example:- parameter n=5, m=5;
assign x= {(n-m){a}}
Friday, January 05, 2001 9:34 pm |
7 |
Peter M. Nyasulu |
Introduction to Verilog
5.9. Conditional Operator: “?”
Conditional operator is like those in C/C++. They evaluate one of the two expressions based on a condition. It will synthesize to a multiplexer (MUX).
Operators |
Example 5 .9 |
x |
y |
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assign a = (g) ? x : y; |
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(cond) ? (result if cond true): |
g |
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1 |
1 |
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assign a = (inc = = 2) ? a+1 : a-1; |
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(result if cond false) |
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/* if (inc), a = a+1, else a = a-1 */ |
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5.10. Operator Precedence
Table 6.1 shows the precedence of operators from highest to lowest. Operators on the same level evaluate from left to right. It is strongly recommended to use parentheses to define order of precedence and improve the readability of your code.
Operator |
Name |
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[ |
] |
bit-select or part-select |
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( |
) |
parenthesis |
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!, ~ |
logical and bit-wise NOT |
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&, |, ~&, ~|, ^, ~^, ^~ |
reduction AND, OR, NAND, NOR, XOR, XNOR; |
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If X=3’B101 and Y=3’B110, then X&Y=3’B100, X^Y=3’B011; |
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+, - |
unary (sign) plus, minus; +17, -7 |
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{ } |
concatenation; {3’B101, 3’B110} = 6’B101110; |
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{{ }} |
replication; {3{3'B110}} = 9'B110110110 |
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*, |
/, |
% |
multiply, divide, modulus; / and % not be supported for synthesis |
+, - |
binary add, subtract. |
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<<, |
>> |
shift left, shift right; X<<2 is multiply by 4 |
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<, |
<=, >, >= |
comparisons. Reg and wire variables are taken as positive numbers. |
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= =, != |
logical equality, logical inequality |
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= = =, != = |
case equality, case inequality; not synthesizable |
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& |
bit-wise AND; AND together all the bits in a word |
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^, ~^, ^~ |
bit-wise XOR, bit-wise XNOR |
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| |
bit-wise OR; AND together all the bits in a word |
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&&, |
logical AND. Treat all variables as False (zero) or True (nonzero). |
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logical OR. (7||0) is (T||F) = 1, (2||-3) is (T||T) =1, |
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|| |
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(3&&0) is (T&&F) = 0. |
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? : |
conditional. x=(cond)? T : F; |
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Table 5.1: Verilog Operators Precedence |
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Friday, January 05, 2001 9:34 pm |
8 |
Peter M. Nyasulu |
Introduction to Verilog
6. Operands
6.1. Literals
Literals are constant-valued operands that can be used in Verilog expressions. The two common Verilog literals are:
(a)String: A string literal is a one-dimensional array of characters enclosed in double quotes (“ “).
(b)Numeric: constant numbers specified in binary, octal, decimal or hexadecimal.
Number Syntax |
Example 6 .1 |
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n’Fddd..., where |
“time is”// string literal |
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n - integer representing number of bits |
267 |
// 32-bit decimal number |
F - one of four possible base formats: |
2’b01 |
// 2-bit binary |
b (binary), o (octal), d (decimal), |
20’hB36F// 20-bit hexadecimal number |
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h (hexadecimal). Default is d. |
‘o62 |
// 32-bit octal number |
dddd- legal digits for the base format
6.2.Wires, Regs, and Parameters
Wires, regs and parameters can also be used as operands in Verilog expressions. These data objects are described in more detail in Sect. 4. .
6.3. Bit-Selects “x[3]” and Part-Selects “x[5:3]”
Bit-selects and part-selects are a selection of a single bit and a group of bits, respectively, from a wire, reg or parameter vector using square brackets “[ ]”. Bit-selects and part-selects can be used as operands in expressions in much the same way that their parent data objects are used.
Syntax
variable_name[index] variable_name[msb:lsb]
Example 6 .2 |
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reg [7:0] a, b; |
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reg [3:0] ls; |
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reg c; |
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c = a[7] & b[7]; |
// bit-selects |
ls = a[7:4] + b[3:0]; |
// part-selects |
6.4. Function Calls
The return value of a function can be used directly in an expression without first assigning it to a register or wire variable. Simply place the function call as one of the operands. Make sure you know the bit width of the return value of the function call. Construction of functions is described in “Functions” on page 19
Syntax
function_name (argument_list)
Example 6 .3
assign a = b & c & chk_bc(c, b);// chk_bc is a function
. . ./* Definition of the function */ function chk_bc;// function definition
input c,b;
chk_bc = b^c; endfunction
Friday, January 05, 2001 9:34 pm |
9 |
Peter M. Nyasulu |