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Introduction to Verilog
Syntax
begin : block_name
reg [msb:lsb] reg_variable_list; integer [msb:lsb] integer_list; parameter [msb:lsb] parameter_list;
... statements ...
end
Example 8 .5
function trivial_one; // The block name is “trivial_one.” input a;
begin: adder_blk; // block named adder, with integer i; // local integer i
... statements ...
end
8.6. for Loops
Similar to for loops in C/C++, they are used to repeatedly execute a statement or block of statements. If the loop contains only one statement, the begin ... end statements may be omitted.
Syntax
for (count = value1;
count </<=/>/>= value2; count = count +/- step)
begin
... statements ...
end
Example 8 .6
for (j = 0; j <= 7; j = j + 1) begin
c[j] = a[j] & b[j]; d[j] = a[j] | b[j];
end
8.7. while Loops
The while loop repeatedly executes a statement or block of statements until the expression in the while statement evaluates to false. To avoid combinational feedback during synthesis, a while loop must be broken with an @(posedge/negedge clock) statement (Section 9.2). For simulation a delay inside the loop will suffice. If the loop contains only one statement, the begin ... end statements may be omitted.
Syntax
while (expression) begin
... statements ...
end
Example 8 .7
while (!overflow) begin @(posedge clk);
a = a + 1; end
8.8. forever Loops
The forever statement executes an infinite loop of a statement or block of statements. To avoid combinational feedback during synthesis, a forever loop must be broken with an @(posedge/negedge clock) statement (Section 9.2). For simulation a delay inside the loop will suffice. If the loop contains only one statement, the begin ... end statements may be omitted. It is
Syntax |
Example 8 .8 |
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forever |
forever begin |
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@(posedge clk); // or use a= #9 a+1; |
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begin |
a = a + 1; |
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... statements ... |
end |
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end |
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8.9. repeat Not synthesizable
The repeat statement executes a statement or block of statements a fixed number of times.
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Peter M. Nyasulu |
Syntax
repeat (number_of_times) begin
... statements ...
end
Introduction to Verilog
Example 8 .9
repeat (2) begin // after 50, a = 00, #50 a = 2’b00; // after 100, a = 01, #50 a = 2’b01; // after 150, a = 00,
end// after 200, a = 01
8.10. disable
Execution of a disable statement terminates a block and passes control to the next statement after the block. It is like the C break statement except it can terminate any loop, not just the one in which it appears.
Disable statements can only be used with named blocks.
Syntax
disable block_name; |
begin: accumulate |
forever |
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begin |
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@(posedge clk); |
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a = a + 1; |
|
if (a == 2’b0111) disable accumulate; |
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end |
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end |
8.11. if ... else if ... else
The if ... else if ... else statements execute a statement or block of statements depending on the result of the expression following the if. If the conditional expressions in all the if’s evaluate to false, then the statements in the else block, if present, are executed.
There can be as many else if statements as required, but only one if block and one else block. If there is one statement in a block, then the begin .. end statements may be omitted.
Both the else if and else statements are optional. However if all possibilities are not specifically covered, synthesis will generated extra latches.
Syntax
if (expression) begin
... statements ...
end
else if (expression) begin
... statements ...
end
... more else if blocks ...
else begin
... statements ...
end
Example 8 .11
if (alu_func == 2’b00) aluout = a + b;
else if (alu_func == 2’b01) aluout = a - b;
else if (alu_func == 2’b10) aluout = a & b;
else // alu_func == 2’b11 aluout = a | b;
if (a == b) // This if with no else will generate begin // a latch for x and ot. This is so they
x = 1; // will hold there old value if (a != b). ot = 4’b1111;
end
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Introduction to Verilog
8.12. case
The case statement allows a multipath branch based on comparing the expression with a list of case choices. Statements in the default block executes when none of the case choice comparisons are true (similar to the else block in the if ... else if ... else). If no comparisons , including delault, are true, synthesizers will generate unwanted latches. Good practice says to make a habit of puting in a default whether you need it or not.
If the defaults are dont cares, define them as ‘x’ and the logic minimizer will treat them as don’t cares. Case choices may be a simple constant or expression, or a comma-separated list of same.
Syntax
case (expression) case_choice1:
begin
... statements ...
end case_choice2:
begin
... statements ...
end
... more case choices blocks ...
default: begin
... statements ...
end endcase
Example 0 .1 case (alu_ctr)
2’b00: aluout = a + b; 2’b01: aluout = a - b; 2’b10: aluout = a & b;
default: aluout = 1’bx; // Treated as don’t cares for endcase // minimum logic generation.
Example 0 .2 case (x, y, z)
2’b00: aluout = a + b; //case if x or y or z is 2’b00.
2’b01: aluout = a - b; 2’b10: aluout = a & b; default: aluout = a | b;
endcase
8.13. casex
In casex(a) the case choices constant “a” may contain z, x or ? which are used as don’t cares for comparison. With case the corresponding simulation variable would have to match a tri-state, unknown, or either signal. In short, case uses x to compare with an unknown signal. Casex uses x as a don’t care which can be used to minimize logic.
Syntax
same as for case statement (Section 8.10)
Example 8 .12 casex (a)
2’b1x: msb = 1; // msb = 1 if a = 10 or a = 11
// If this were case(a) then only a=1x would match. default: msb = 0;
endcase
8.14. casez
Casez is the same as casex except only ? and z (not x) are used in the case choice constants as don’t cares. Casez is favored over casex since in simulation, an inadvertent x signal, will not be matched by a 0 or 1 in the case choice.
Syntax
same as for case statement (Section 8.10)
Example 8 .13
casez (d)
3’b1??: b = 2’b11; // b = 11 if d = 100 or greater
3’b01?: b = 2’b10; // b = 10 if d = 010 or 011 default: b = 2’b00;
endcase
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Introduction to Verilog
9. Timing Controls
9.1. Delay Control Not synthesizable
This specifies the delay time units before a statement is executed during simulation. A delay time of zero can also be specified to force the statement to the end of the list of statements to be evaluated at the current simulation time.
Syntax |
Example 9 .1 |
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#delay statement; |
#5 a = b + c; |
// evaluated and assigned after 5 time units |
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#0 a = b + c; |
// very last statement to be evaluated |
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9.2. Event Control, @
This causes a statement or begin-end block to be executed only after specified events occur. An event is a change in a variable. and the change may be: a positive edge, a negative edge, or either (a level change), and is specified by the keyword posedge, negedge, or no keyword respectively. Several events can be combined with the or keyword. Event specification begins with the character @and are usually used in always statements. See page 18.
For synthesis one cannot combine level and edge changes in the same list.
For flip-flop and register synthesis the standard list contains only a clock and an optional reset.
For synthesis to give combinational logic, the list must specify only level changes and must contain all the variables appearing in the right-hand-side of statements in the block.
Syntax
@(posedge variable or negedge variable) statement;
@(variable or variable . . .) statement;
Example 9 .2 always
@(posedge clk or negedge rst)
if (rst) Q=0; else Q=D; // Definition for a D flip-flop.
@(a or b or e); |
// re-evaluate if a or b or e changes. |
sum = a + b + e; |
// Will synthesize to a combinational adder. |
9.3. Wait Statement Not synthesizable
The wait statement makes the simulator wait to execute the statement(s) following the wait until the specified condition evaluates to true. Not supported for synthesis.
Syntax |
Example 9 .3 |
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wait (condition_expression) statement; |
wait (!c) a = b; // wait until c=0, then assign b to a |
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9.4. Intra-Assignment Delay Not synthesizable
This delay # is placed after the equal sign. The left-hand assignment is delayed by the specified time units, but the right-hand side of the assignment is evaluated before the delay instead of after the delay. This is important when a variable may be changed in a concurrent procedure. See also “Delay in Assignment (not for synthesis)” on page 12.
Syntax
variable = # t expression;
Example 9 .4
assign a=1; assign b=0; always @(posedge clk)
b = #5 a; // a = b after 5 time units. always @(posedge clk)
c = #5 b; /* b was grabbed in this parallel procedure before the first procedure changed it. */
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Introduction to Verilog
10. Procedures: Always and Initial Blocks
10.1. Always Block
The always block is the primary construct in RTL modeling. Like the continuous assignment, it is a concurrent statement that is continuously executed during simulation. This also means that all always blocks in a module execute simultaneously. This is very unlike conventional programming languages, in which all statements execute sequentially. The always block can be used to imply latches, flip-flops or combinational logic. If the statements in the always block are enclosed within begin ... end, the statements are executed sequentially. If enclosed within the fork
... join, they are executed concurrently (simulation only).
The always block is triggered to execute by the level, positive edge or negative edge of one or more signals (separate signals by the keyword or). A double-edge trigger is implied if you include a signal in the event list of the always statement. The single edge-triggers are specified by posedge and negedge keywords.
Procedures can be named. In simulation one can disable named blocks. For synthesis it is mainly used as a comment.
Syntax 1
always @(event_1 or event_2 or ...) begin
... statements ...
end
Syntax 2
always @(event_1 or event_2 or ...) begin: name_for_block
... statements ...
end
Example 10 .1
always @(a or b) // level-triggered; if a or b changes levels always @(posedge clk); // edge-triggered: on +ve edge of clk
see previous sections for complete examples
10.2. Initial Block
The initial block is like the always block except that it is executed only once at the beginning of the simulation. It is typically used to initialize variables and specify signal waveforms during simulation. Initial blocks are not supported for synthesis.
Syntax
initial begin
... statements ...
end
Example 10 .2
inital begin
clr = 0; // variables initialized at
clk = 1; // beginning of the simulation end
inital |
// specify simulation waveforms |
begin |
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a = 2’b00; |
// at time = 0, a = 00 |
#50 a = 2’b01; |
// at time = 50, a = 01 |
#50 a = 2’b10; |
// at time = 100, a = 10 |
end |
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Peter M. Nyasulu |