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Introduction to Verilog
7. Modules
7.1. Module Declaration
A module is the principal design entity in Verilog. The first line of a module declaration specifies the name and port list (arguments). The next few lines specifies the i/o type (input, output or inout, see Sect. 4.4. ) and width of each port. The default port width is 1 bit.
Then the port variables must be declared wire, wand,. . ., reg (See Sect. 4. ). The default is wire. Typically inputs are wire since their data is latched outside the module. Outputs are type reg if their signals were stored inside an always or initial block (See Sect. 10. ).
Syntax
module module_name (port_list); input [msb:lsb] input_port_list; output [msb:lsb] output_port_list; inout [msb:lsb] inout_port_list;
... statements ...
endmodule
Example 7 .1
module add_sub(add, in1, in2, oot); input add; // defaults to wire input [7:0] in1, in2; wire in1, in2; output [7:0] oot; reg oot;
... statements ...
endmodule
add |
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in1 |
oot |
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8 |
add_sub |
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in2 |
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8 |
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8 |
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7.2. Continuous Assignment
The continuous assignment is used to assign a value onto a wire in a module. It is the normal assignment outside of always or initial blocks (See Sect. 10. ). Continuous assignment is done with an explicit assign statement or by assigning a value to a wire during its declaration. Note that continuous assignment statements are concurrent and are continuously executed during simulation. The order of assign statements does not matter. Any change in any of the right-hand-side inputs will immediately change a left-hand-side output.
Syntax
wire wire_variable = value; assign wire_variable = expression;
Example 7 .2 |
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wire [1:0] a = 2’b01; // assigned on declaration |
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assign b = c & d; |
// using assign statement |
c |
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assign d = x | y; |
x |
b |
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/* The order of the assign statements |
d |
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y |
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does not matter. */ |
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7.3. Module Instantiations
Module declarations are templates from which one creates actual objects (instantiations). Modules are instantiated inside other modules, and each instantiation creates a unique object from the template. The exception is the top-level module which is its own instantiation.
The instantiated module’s ports must be matched to those defined in the template. This is specified:
(i) by name, using a dot(.) “ .template_port_name (name_of_wire_connected_to_port)”.
or(ii) by position, placing the ports in exactly the same positions in the port lists of both the template and the instance.
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Peter M. Nyasulu |
Introduction to Verilog
Syntax for Instantiation |
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Example 7 .3 |
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module_name |
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instance_name_1 (port_connection_list), |
// MODULE DEFINITION |
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instance_name_2 (port_connection_list), |
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...... |
module and4(a, b, c); |
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instance_name_n (port_connection_list); |
input [3:0] a, b; |
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output [3:0] c; |
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assign c = a & b; |
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endmodule |
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// MODULE INSTANTIATIONS wire [3:0] in1, in2; wire [3:0] o1, o2;
/* C1 is an instance of module and4 C1 ports referenced by position */ and4 C1 (in1, in2, o1);
/* C2 is another instance of and4. C2 ports are referenced to the declaration by name. */
and4 C2 (.c(o2), .a(in1), .b(in2));
Modules may not be instantiated inside procedural blocks. See “Procedures: Always and Initial Blocks” on page 18.
7.4. Parameterized Modules
You can build modules that are parameterized and specify the value of the parameter at each instantiation of the module. See “Parameter” on page 5 for the use of parameters inside a module. Primitive gates have parameters which have been predefined as delays. See “Basic Gates” on page 3.
Syntax
module_name #(parameter_values) instance_name(port_connection_list);
Example 7 .4
// MODULE DEFINITION |
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module shift_n (it, ot); |
// used in module test_shift. |
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input [7:0] it; |
output [7:0] ot; |
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parameter n = 2;‘ |
// default value of n is 2 |
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assign ot = (it << n); |
// it |
shifted left n times |
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endmodule |
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// PARAMETERIZED INSTANTIATIONS |
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wire [7:0] in1, |
ot1, ot2, ot3; |
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shift_n |
shft2(in1, |
ot1), |
// shift by 2; default |
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shift_n |
#(3) shft3(in1, ot2); |
// shift by 3; override parameter 2. |
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shift_n |
#(5) shft5(in1, ot3); |
// shift by 5; override parameter 2. |
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Synthesis does not support the defparam keyword which is an alternate way of changing parameters.
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Introduction to Verilog
c
8. Behavioral Modeling
Verilog has four levels of modelling:
1)The switch level which includes MOS transistors modelled as switches. This is not discussed here.
2)The gate level. See “Gate-Level Modelling” on p. 3
3)The Data-Flow level. See Example 7 .4 on page 11
4)The Behavioral or procedural level described below.
Verilog procedural statements are used to model a design at a higher level of abstraction than the other levels. They provide powerful ways of doing complex designs. However small changes n coding methods can cause large changes in the hardware generated. Procedural statements can only be used in procedures. Verilog procedures are described later in “Procedures: Always and Initial Blocks” on page 18,“Functions” on page 19, and “Tasks Not Synthesizable” on page 21.
8.1. Procedural Assignments
Procedural assignments are assignment statements used within Verilog procedures (always and initial blocks). Only reg variables and integers (and their bit/part-selects and concatenations) can be placed left of the “=” in procedures. The right hand side of the assignment is an expression which may use any of the operator types described in Sect. 5.
8.2. Delay in Assignment (not for synthesis)
In a delayed assignment t time units pass before the statement is executed and the left-hand assignment is made. With intra-assignment delay, the right side is evaluated immediately but there is a delay of t before the result is place in the left hand assignment. If another procedure changes a right-hand side signal during t, it does not effect the output. Delays are not supported by synthesis tools.
Syntax for Procedural Assignment variable = expression
Delayed assignment
# t variable = expression;
Intra-assignment delay variable = # t expression;
Example 8 .1
reg [6:0] sum; reg h, ziltch; sum[7] = b[7] ^ c[7]; // execute now.
ziltch = #15 ckz&h; /* ckz&a evaluated now; ziltch changed after 15 time units. */
#10 hat = b&c; /* 10 units after ziltch changes, b&c is evaluated and hat changes. */
8.3. Blocking Assignments
Procedural (blocking) assignments (=) are done sequentially in the order the statements are written. A second assignment is not started until the preceding one is complete. See also Sect. 9.4.
Syntax
Blocking
variable = expression; variable = # t expression; grab inputs now, deliver ans.
later.
# t variable = expression; grab inputs later, deliver ans.
later
Example 8 .2. For simulation |
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initial |
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begin |
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a=1; b=2; |
c=3; |
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#5 a = b + c; |
// wait for 5 units, and execute a= b + c =5. |
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d = a; |
// Time continues from last line, d=5 = b+c |
at t=5. |
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Example 0 .1. For synthesis |
X |
Y |
Z |
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1D |
1D |
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always @( posedge clk) |
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C1 |
C1 |
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begin |
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Z=Y; Y=X; // shift register |
x |
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y |
z |
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y=x; z=y; //parallel ff. |
1D |
1D |
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C1 |
C1 |
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Introduction to Verilog
8.4. Nonblocking (RTL) Assignments (see below for synthesis)
RTL (nonblocking) assignments (<=), which follow each other in the code, are done in parallel. The right hand side of nonblocking assignments is evaluated starting from the completion of the last blocking assignment or if none, the start of the procedure. The transfer to the left hand side is made according to the delays. A delay in a non-blocking statement will not delay the start of any subsequent statement blocking or non-blocking.
A good habit is to use “<=” if the same variable appears on both sides of the equal sign (Example 0 .1 on page 13).
For synthesis
•One must not mix “<=” or “=” in the same procedure.
•“<=” best mimics what physical flip-flops do; use it for “always @ (posedge clk ..) type procedures.
•“=” best corresponds to what c/c++ code would do; use it for combinational procedures.
:
Syntax
Non-Blocking
variable <= expression; variable <= # t expression;
# t variable <= expression;
Example 0 .1. For simulation |
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initial |
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begin |
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#3 b <= a; |
/* grab a at t=0 Deliver b at t=3. |
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#6 x <= b + c; |
// grab b+c at t=0, wait and assign x at t=6. |
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x is unaffected by b’s change. */ |
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Example 0 .2. For synthesis |
X |
Y |
Z |
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always @( posedge clk) |
1D |
1D |
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begin |
C1 |
C1 |
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Z<=Y; Y<=X; // shift register |
x |
y |
z |
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1D |
1D |
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y<=x; z<=y; //also a shift register. |
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C1 |
C1 |
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Example 8 .3. Use <= to transform a variable into itself. reg G[7:0];
always @( posedge clk)
G <= { G[6:0], G[7]}; // End around rotate 8-bit register.
The following example shows interactions between blocking and non-blocking for simulation. Do not mix the two types in one procedure for synthesis.
Syntax
Non-Blocking
variable <= expression; variable <= # t expression; ?# t variable <=expression;
Blocking
variable = expression; variable = # t expression;
# t variable = expression;
Example 8 .4 for simulation only
initial begin |
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a=1; b=2; |
c=3; x=4; |
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#5 |
a = b + c; |
// wait for 5 units, then grab b,c and execute a=2+3. |
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d = a; |
// Time continues from last line, d=5 = b+c at t=5. |
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x <= #6 |
b + c;// grab b+c now at t=5, don’t stop, make x=5 at t=11. |
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b <= #2 |
a; |
/* grab a at t=5 (end of last blocking statement). |
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Deliver b=5 at t=7. previous x is unaffected by b change. */ |
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y <= #1 |
b + c;// grab b+c at t=5, don’t stop, make x=5 at t=6. |
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#3 |
z = b + c; |
// grab b+c at t=8 (#5+#3), make z=5 at t=8. |
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w <= x |
// make w=4 at t=8. Starting at last blocking assignm. |
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8.5. begin ... end
begin ... end block statements are used to group several statements for use where one statement is syntactically allowed. Such places include functions, always and initial blocks, if, case and for statements. Blocks can optionally be named. See “disable” on page 15) and can include register, integer and parameter declarations.
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Peter M. Nyasulu |