Файл: Real-time processing with the Philips LPC ARM mcu using GCC and uCOS II RTOS (D.W. Hawkins, 2006).pdf

Real-time processing with the Philips LPC ARM microcontroller; using GCC and the MicroC/OS-II RTOS.

Philips 05: Project Number AR1803

D. W. Hawkins (dwh@ovro.caltech.edu)

May 10, 2006

Contents

3.4Examples 4(a), (b), and (c): C programs with .bss, .data, and .rodata sections . . 13

3.5 Example 5: LPC2138 processor initialization . . . . . . . . . . . . . . . . . . . . . . 19

3.5.1PLL setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

3.5.2MAM setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

3.5.3 Stacks setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

3.6Example 6: Exception handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

3.9Example 9: Multiple interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

4.1ARM-GCC port description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

4.1.1Port header; os cpu.h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

4.1.2Port C-functions; os cpu c.c . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

4.2Port testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

4.2.1Test 1: Task-to-IRQ context switching . . . . . . . . . . . . . . . . . . . . . . 43

4.2.2Test 2: Task-to-task context switching . . . . . . . . . . . . . . . . . . . . . . 44

4.2.3Test 3: IRQ-FIQ interrupt nesting . . . . . . . . . . . . . . . . . . . . . . . . 44

4.2.4Test 4: IRQ interrupt nesting . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

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1 Introduction

The ARM processor is a reduced instruction set computer (RISC) intellectual property (IP) core defined by Advanced RISC Machines, Ltd (ARM). The ARM CPU architectures widely available today are based on the version 4 and 5 architectures [12]. ARM processor cores are used by Intel (StrongARM and XScale processors), Sharp, Atmel, Philips, Analog Devices, and many other semiconductor manufacturers.

The ARM processor can operate with two instruction sets; ARM mode, and THUMB mode. The ARM mode uses a 32-bit instruction set, while THUMB mode uses a 16-bit instruction set. The use of THUMB mode reduces the execution speed of the code, but reduces the memory requirements of the code, so finds use in the microcontroller applications of the processor core.

µCOS-II is a real-time operating system (RTOS) written by Jean Labrosse and supported by his company Micrium. The RTOS is well described in his book [6]. The RTOS defines a standard set of operating system (OS) primitives and the book defines how to port the RTOS to di erent processor architectures. This document describes a port for the ARM processor operating in 32-bit mode for the GNU GCC compiler.

The following references provide additional resources on ARM processors and µCOS-II RTOS:

•“ARM system-on-chip architecture”, S. Furber [5].

•“ARM Architecture Reference Manual”, D. Seal [12]. Chapters A1 and A2 provide an overview of the ARM architecture and programming model.

•“ARM System Developer’s Guide”, A. Sloss et al [13]

•“MicroC/OS-II: The real-time kernel”, J. Labrosse [6].

Author’s Note: May 10, 2006.

This document and the associated code were submitted to the Circuit Cellar Philips ARM 2005 contest. The project was selected for a Distinctive Excellence award. At some point Circuit Cellar are going to put the project files up on their web site.

Prior to the ARM 2005 contest I’d never used the ARM processor. My initial objective was to understand the code generated and required by GCC to link microcontroller applications, and then use that knowledge to port the uCOS-II RTOS to the processor. I’d played with the Atmel AVR and WinAVR for the Circuit Cellar Atmel AVR 2004 contest, but had simply used WinAVR, not appreciating the task done by the startup files and the AVR standard library. Many of the examples in this project are stand-alone, in that the code provides the start-up routines and the application code (some of the code in subfolders is repeated for the sake of simplification).

Please excuse the poor makefiles and anything else you find over-simplified, I was just playing and didn’t really anticipate too many people looking at the code. However, it seems alot of the questions asked on the LPC2000 news group could be answered by this document, so feel free to provide feedback, or modified code, and I’ll update the original source and re-release the code as it is updated. I plan to go though and add more sections, and get newlib-lpc up-and-running, but for now, this will have to do.

Feel free to post comments to the LPC2000 news group, I read it.

Cheers,

Dave Hawkins, Caltech. dwh@ovro.caltech.edu.

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Figure 1: ARM programming modes. In ARM-mode the processor can switch between seven operating modes. The processor has a set of banked registers, i.e., the actual register an instruction accesses is dependent on the operating mode. The greyed registers in the figure show the physically di erent registers in each operating mode.

2 Programmers Model

Figure 1 shows the ARM programming model (Chapter A2 [12], p39 [5], p7 [7]), and the seven ARM operating modes. A general purpose operating system such as Linux uses the User mode of the processor for user-space processes, and the Supervisor mode for the operating system kernel. For a real-time OS, such as µCOS-II, the kernel and application tasks run in Supervisor mode. Exception modes need to be dealt with appropriately in either a general purpose OS (by kernel routines) or in an RTOS. The seven processor modes are (pA2-3 [12], pA2-11 [12] has the 5-bit values for each mode);

In any of the seven operating modes shown in Figure 1, code has access to 16 general-purpose registers, R0 through R15, and a current program status register (CPSR). In exception modes there is an additional register, called the saved program status register (SPSR), which has identical bits to the CPSR. The processor has a set of banked registers, where dependent on the operating mode

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Figure 2: Control and program status register (CPSR) bits. The defined bits are the flags; negative, zero, carry, and overflow, and the control bits; IRQ disable, FIQ disable, ARM/THUMB instruction mode, and the 5-bit processor operating mode (where the modes are shown in Figure 1).

the physical register accessed can be di erent. For example in fast interrupt mode (FIQ) registers R8 through R14 are unique for that mode so do not need saving through interrupt context switches. Register R13 is conventionally used as the Stack Pointer (pA2-6 [12]), while registers R14 and R15 have special roles as the Link Register (return address), and Program Counter (pA1-3 [12]). The ARM procedure calling standard (APCS) defines the recommended use of the other registers for passing arguments and return variables.

Stack pointer

The stack grows from high-to-low.

Link register

The link register holds the address of the next instruction after a Branch and Link (BL) instruction which is the instruction used to make a subroutine call. At all other times, R14 can be used as a general-purpose register (pA1-3 [12]). To return from a subroutine call, the link register is copied into the program counter register (pA1-4 [12]). If nested of interrupts is used, special care of the link register contents is required (pA2-6 [12]).

Program counter

When an instruction reads the program counter, the value read is the address of the instruction plus 8 (4 bytes if operating in THUMB mode). The program counter is 32-bit aligned (bits 1 and 0 are always zero) in ARM mode, and 16-bit aligned in THUMB mode (bit 0 is zero) (pA1-3 [12]).

Status registers

The CPSR (and SPSR) contains four sections; flags, status, extension, and control. These sections and bits are shown in Figure 2. There are specific instructions for transferring the status registers to and from the general purpose registers.

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3 ARM GCC

An embedded systems C-coded application consists of assembly-coded startup code containing processor and run-time environment (eg. stacks) initialization, the C-coded application, staticallylinked library code (newlib and user libraries), and a linker script defining the device memory map and code load and run addresses. The GNU Compiler Collection (GCC) for the ARM processor can be downloaded from www.gnuarm.com, or can be built from source as described in Appendix A. The following sections walk-through increasingly complex examples to demonstrate the GCC tools.

The examples in the following sections are developed for a Keil MCB2130 development board containing a Philips LPC2138 ARM microcontroller. The Keil MC2130 evaluation board contains a set of LEDs connected to pins P1.[16..23]. The examples use the LEDs to provide visual feedback that the example program operates correctly.

3.1Example 1: Basic startup assembler

/ ex1 . s /

−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−

/

. t e x t

. arm

. g l o b a l s t a r t s t a r t :

/ Vectors (8 t o t a l ) /

bl o o p / IRQ /

bl o o p / FIQ /

/ −−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−

Test code

−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−

/

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