Файл: Single- and Multi-Chip Microcontroller Interfacing For the Motorola 68HC12 (G.J. Lipovski, 1999).pdf
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ii |
Contents |
10. Display and Storage Systems |
445 |
10.1 Display Systems |
446 |
10.1.1 NTSC Television Signals |
446 |
10.1.2 A 6812 SPI Display |
448 |
10.1.3 A Bitmapped Display |
450 |
10.1.4 An Object-oriented Display |
453 |
10.2 Storage Systems |
455 |
10.2.1 Floppy Disk Format |
455 |
10.2.2. The Western Digital 37C65C Floppy Disk Controller |
459 |
10.2.3. Floppy Disk Interfacing Procedures |
462 |
10.2.4 Personal Computer Disk Data Organization |
466 |
10.2.5 Object-oriented Disk I/O |
470 |
10.3 Conclusions |
473 |
Problems |
475 |
Appendix. Using the HIWAVE CD-ROM |
481 |
Index |
483 |
Preface
By 1980, the microcomputer had changed so many aspects of engineering that the cliche "microcomputer revolution" echoed from almost every other magazine article and earned paper in the field. It is a great tool. This book's ancestor, Microcomputer nterfacing: Principles and Practices, was written at that time to establish some design heory for this dynamic field. A successor book, which is this book's predecessor,
Singleand Multiple-Chip Microcomputer Interfacing, was motivated by two significant changes: the evolution of powerful single-chip microcomputers and the IEEE Computer Society Curriculum Committee recommendation for a course on microcomputer interfacing and communication. The development of powerful single-chip microcomputers introduces a new design choice: to use either a microprocessor in a personal computer with some 16M bytes of memory and an operating system or a less costly single-chip microcomputer with much less overhead. This decision is largely based on the designer's understanding of the capabilities and limitations of the singlechip microcomputer. The development of a standard curriculumfor a course lent stability o this field. The book aimed to teach the principles and practices of microcomputer systems design in general, and interfacing in particular, and to foster an understanding of single-chip microcomputers within the guidelines of the IEEE Computer Society Curriculum Committee's recommendations. This book was motivated by the development of the Motorola 6812, and its need for more sophisticated software. Since he 6812 featured so many on-chip I/O devices, which were already connected to the 6812's address and data buses, but which each had to be programmed, and managing a number of I/O devices often necessitated the use of time sharing, this book features programming in C and C++.However, the designer must be wary of high-level language statements that do not do what he or she intended. High-level languages are designed for algorithms, not for I/O interfacing, and optimizing high-level language compilers can "optimize you right out of business." The designer is shown how each high-level anguage statement is implemented in assembler language.
This book's predecessor evolved from a set of notes for a senior level course in microcomputer design. The course - which is still taught - focuses on the combined hardware/software design of microcomputer systems. It emphasizes principles of design because theory is as necessary for a solid foundation in design as theory is in any engineering discipline. However, it also emphasizes the practices - the details of howto get a system to work - because microcomputer system design requires hands-on experience. There is a remarkable difference between a student who merely reads about microcomputers and a student who has worked with one - clear evidence that theory has o be taught with practice. Practical experience is desirable in almost any engineering course. This is not always possible. But microcomputer systems are inexpensive enough hat the school or the student can afford this hands-on opportunity; and the joy of seeing he principles work is so attractive that the student often can't get enough of the material o be satiated. The development of very powerful, inexpensive single-chip microcomputers furthers this opportunity. So the course, this book's predecessor, and his book, all emphasize both the principles and practices of microcomputer design.
List of Figures
Figure |
Title |
Page |
Figure 1,1. |
Analogy to the von Neumann Computer |
3 |
Figure 1.2. |
Registers in the 6812 |
13 |
Figure 1.3, |
Block Diagram Showing the Effect of an Instruction |
31 |
Figure 1.4. |
Organization of a von Neumann Computer |
32 |
Figure 1.5. |
Single-Chip Mode of the MC68HC812A4 |
32 |
Figure 1.6. |
Expanded Wide Multiplexed Bus Mode of the MC68HC812A4 |
33 |
Figure 1.7. |
Single-Chip Mode of the MC68HC912B32 |
34 |
Figure 1.8. |
Expanded Wide Multiplexed Bus Mode of the MC68HC912B32 |
34 |
Figure 1.9. |
Memory Map of 6812 Microcontrollers |
35 |
Figure 2.1. |
Conditional Statements |
50 |
Figure 2.2. |
Case Statements |
52 |
Figure 2.3. |
Loop Statements |
53 |
Figure 2.4. |
A Huffman Coding Tree |
62 |
Figure 2.5. |
An Object and its Pointers |
78 |
Figure 2.6. |
Other Huffman Codes |
88 |
Figure 3.1. |
Voltage Waveforms, Signals, and Variables |
94 |
Figure 3.2. |
Some Common Gates |
98 |
Figure 3.3. |
Logic Diagrams for a Popular Driver and Register |
99 |
Figure 3.4. |
16R4 PAL Used in Microcomputer Designs |
103 |
Figure 3.5. |
Some Timing Relationships |
105 |
Figure 3.6. |
Timing Relationships for the MC68HC812A4 |
105 |
Figure 3,7. |
Timing Relationships for the MC68HC912B32 |
107 |
Figure 3.8. |
Address and Data Bus Signals |
109 |
Figure 3.9. |
Decoding for Table 3.1 |
110 |
Figure 3.10. |
Common Integrated Circuits Used in Decoders |
111 |
Figure 3.11. |
Logic Design of Minimal Complete Decoder |
112 |
Figure 3.12. |
A 74HC74 |
116 |
Figure 3.13. |
Some MSI I/O Chips |
117 |
Figure 4.1. |
Logic Diagrams for I/O Devices for a Narrow Expanded Bus |
124 |
Figure 4.2. |
A Readable Output Port for a Narrow Expanded Bus |
124 |
Figure 4.3. An Unusual I/O Port |
127 |
|
Figure 4.4. |
A Set Port |
129 |
Figure 4.5. |
Address Output Techniques |
130 |
Figure 4.6. |
MC68HC812A4 Parallel I/O Ports. |
138 |
Figure 4.7. |
MC68HC812A4 Parallel I/O Control Ports |
139 |
Figure 4.7. |
MC68HC912B32 Parallel I/O Ports |
140 |
Figure 4.9. |
MC68HC812B32 Parallel I/O Control Ports |
141 |
Figure 4.10. |
Traffic Light |
148 |
Figure 4.11. |
Mealy Sequential Machine |
151 |
xvn
Hi |
List of Figures |
|
gure 4.12. |
A Linked-List Structure |
152 |
gure 4.13. |
Connections for a Chip Tester |
154 |
gure 4.14. |
The74HCOO |
155 |
gure 4.15. |
M68ISA Time-of-Day Chip |
163 |
gure 4.16. |
Connections to an LCD Display |
165 |
gure 4.17. |
Simple Serial Input/Output Ports |
167 |
gure 4.18. |
Configurations of Simple Serial Input/Output Registers |
168 |
gure 4.19. |
Flow Chart for Series Serial Data Output |
170 |
gure 4.20. |
Dallas Semiconductor 1620 Digital Thermometer |
171 |
gure 4.21. |
SPI Data, Control, and Status Ports |
173 |
gure 4.22. |
Multicomputer Communication System Using the SPI |
174 |
gure 4.23. |
Some ICs for I/O |
185 |
gure 5.1. |
Paper Tape Hardware |
194 |
gure 5.2. |
State Diagram for I/O Devices |
195 |
gure 5.3. |
Flow charts for Programmed I/O |
198 |
gure 5.4. |
Key Wakeup Ports for the MC68HC812A4 |
199 |
gure 5.5. |
Infrared Control |
202 |
gure 5.6. |
Magnetic Card Reader |
202 |
gure 5.7. |
BSRX-10 |
203 |
gure 5.8. |
Key Wakeup Interrupt Request Path |
210 |
gure 5.9. |
IRQ Interrupt Request Path |
213 |
gure 5.10. |
MC68HC812A4 Polled Interrupt Request Path |
224 |
gure 5.11. |
MC68HC912B32 Polled Interrupt Request Path |
225 |
gure 5.12. |
Flow Chart for Round-robin Interrupt Polling |
226 |
gure 5.13. |
MC68HC812A4 Vector Interrupt Request Path |
229 |
gure 5.14. |
MC68HC912B32 Vector Interrupt Request Path |
230 |
gure 5.15. |
Keys and Keyboards |
232 |
gure 5.16. |
SPI Network |
235 |
gure 5.17. |
Bar Code Frames |
236 |
gure 5.18. |
X-10 Frame |
242 |
gure 5.19. |
Periodic Interrupt Device |
244 |
gure 5.20. |
Centronics Parallel Printer Port |
250 |
gure 5.21. |
Connections for Context Switching |
261 |
gure 5.22. |
Fast Synchronization Mechanisms Using Memory Organizations |
263 |
gure 5.23. |
Indirect Memory Using an MCM6264D-45 |
264 |
gure 5.24. |
Synchronization Mechanisms Summarized |
267 |
gure 5.25. |
74HC266 |
271 |
gure 6.1. |
MC68HC812A4 Mode Port |
278 |
gure 6.2. |
Memory Maps |
278 |
gure 6.3. |
MC68HC812A4 Port E Assignment Register |
280 |
gure 6.4. |
MC68HC812A4 Internal Memory Map Control Ports |
280 |
gure 6.5. |
MC68HC812A4 Chip Select Memory Map |
281 |
gure 6.6. |
MC68HC812A4 Chip Select Registers |
282 |
gure 6.7. |
Use of Chip Select Lines |
282 |
gure 6.8. |
MC68HC812A4 Memory Expansion Ports |
284 |
List of Figures |
xix |
||
Figure 6.9. |
MC68HC812A4 Memory Expansion Mapping |
285 |
|
Figure 6.10. |
MC68HC812A4 EEPROM Control Ports |
287 |
|
Figure 6,11. |
MC68HC912B32 Flash Control Ports |
288 |
|
Figure 6.12. |
MC68HC812A4 Clock Control |
289 |
|
Figure 6.13. |
An MCM6264D-45 Memory System |
29! |
|
Figure 6.14. |
Analysis of Memory Timing |
292 |
|
Figure 6.15. |
MC68HC912B32 Address Demultiplexing |
293 |
|
Figure 6.16. |
8K-by-16-bitWordWide Expanded Mode Memory System |
294 |
|
Figure 6.17. |
BackgroundDebug Module |
295 |
|
Figure 7.1. |
Waveforms of Alternating Voltage Signals |
307 |
|
Figure 7,2. |
Position Transducers |
310 |
|
Figure 7.3. |
Power OutputDevices |
315 |
|
Figure 7.4. |
Triac Control Techniques |
316 |
|
Figure 7.5. |
OperationalAmplifierCircuits |
318 |
|
Figure 7.6. |
Analog Switches |
320 |
|
Figure 7.7. |
A Practical Voltage Follower |
324 |
|
Figure 7.8. |
Practical Analog Switches |
325 |
|
Figure 7.9. |
555 Timer |
326 |
|
Figure 7.10. |
Some Filters |
328 |
|
Figure 7.11. |
Selecting Inputs for a Stereo Preamplifier |
329 |
|
Figure 7.12. |
Computer Control of Amplification |
331 |
|
Figure |
7.13. |
Nonlinear Signal Conditioning |
333 |
Figure 7.14. |
D-to-A Converters |
336 |
|
Figure 7.15. |
The Crystal Semiconductor CS4330 |
337 |
|
Figure 7.16. |
A-to-D Converters |
339 |
|
Figure 7.17. |
Frequency-to-Voltage Conversion |
342 |
|
Figure 7.18. |
Voltage-to-Frequency Conversion |
342 |
|
Figure 7.19. |
Phase-locked Loop |
344 |
|
Figure 7.20. |
Data Acquisition System |
345 |
|
Figure 7.21. |
Serial InterfaceA-to-D Converter |
347 |
|
Figure 7.22. |
A-to-D Subsystem of the MC68HC812A4 |
348 |
|
Figure 7.23. |
The Spline Technique |
35! |
|
Figure 7.24. |
Feedback Control |
351 |
|
Figure |
7.25. |
Some OP AMP Circuits |
356 |
Figure |
8.1. |
The Counter/Timer Subsystem |
363 |
Figure 8.2. |
Output Compare Logic |
364 |
|
Figure 8.3. |
Pulse-Width Module Ports |
367 |
|
Figure |
8.4. |
A Touch-Tone Generator |
371 |
Figure 8.5. Timing of Some Pulses |
377 |
||
Figure |
8.6. |
Output Compare 7 Ports |
377 |
Figure 8.7. |
Input Capture |
382 |
|
Figure |
8.8. |
The Pulse Accumulator |
386 |