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82 The Quintessential PIC Microcontroller

In terms of architecture, referring back to Figs. 3.1 and 3.2 on pages 42 and 44 respectively, the microprocessor is the central processor unit, whereas the microcontroller is the complete functioning computer-like system. As an example, consider the electronics of a car odometer monitoring system displaying total distance since manufacture and also a trip odometer. The main system input signal is a tachometer generating pulses on each rotation of the engine flywheel, which when totalized gives the number of engine revolutions – and the pulse to pulse duration could also give the road speed. Of course the actual road distance depends on the gearing of the engine, and thus we need to know which of the five gear ratios has been chosen by the driver at any time. This is shown as five lines G1…G5 originating from the gear box. One signal will be high for the appropriate forward gear, with neutral and reverse being ignored. Additional inputs are used to give a manufacturer’s option of a mile or kilometer display, and a user input to reset the trip display to zero.

The display itself consists of seven 7-segment digits (see Fig. 6.6 on page 148) to indicate up to (optimistically) .. As there are so many segments to control (49 in total), Fig. 4.1 shows the display data fed via a single digital line, shunted serially into a shift register – see Fig. 2.20 on page 36. A second line provides clock pulses for the register with 49 clock pulses being needed to refresh the display.15

The trip odometer display comprises four digits, which will record up to .. Similarly two output lines are used to feed and clock the shift register, and 28 clock pulses are needed to shift in a new 4-digit trip display.

The resource budget (list of subsystem functions) for this system is:

•An edge-triggered input for the tachometer pulse train, connected to a counter/timer to totalize engine revolutions.

•Seven static digital input lines to interface to the gear ratio, mi/km option and trip reset.

•Four output digital lines to clock the two shift registers and provide segment data.

•A microprocessor to do the calculations and to read/write to the input/ output ports respectively.

•Program memory, usually ROM of some kind.

•Data memory for temporary storage of program variables, usually static RAM.

•Non-volatile storage for physical variables, such as total distance and distance since trip reset.

This functionality could be implemented onto a single integrated circuit, and in this situation would be known as a microcontroller, that is a mi-

15Many displays have this shift register built in as a complete subsystem.

4. The PIC16F84 Microcontroller 83

croprocessor integrated with its support circuitry giving a complete microcomputer function. Of course the resource budget listed above is specific to our example. Although the core functions (microprocessor and memory) are common to a wide range of applications, the input/output (I/O) interface needs to be tailored to the task in hand. Some typical I/O functions are:

•I/O to interface to a serial bit stream of various synchronous and asynchronous protocols.

•Counter/timer functions to totalize input events and to generate precision time-varying digital output signals.

•Analog to digital multiplex/conversion to be able to read and digitize analog inputs.

•Digital to analog conversion to output analog signals.

•Display ports to drive multi-digit liquid crystal displays.

This alternative approach to using additional silicon resources led to the first MCUs in the late 1970s. For example the 35,000 transistor Motorola 6801, designed in response to a specific application from an car manufacturer, used the existing 6800 MPU as a core, with 2048 bytes of ROM program memory, 128 bytes of data RAM, 29 I/O lines and a 16bit timer. With the viability of the MCU approach vindicated, a range of families, each based on a specific core but with individual family members having a di erent selection of I/O facilities, was introduced by the leading MPU manufacturers. For example, the Motorola 68HC11 family (a development of the 6801 MCU) uses a slightly enhanced 6800 core. The 68HC12 and 68HC16 families use 16-bit cores but are designed to be upwardly compatible with the 8-bit 68HC11. It was quickly realised that many embedded applications did not even need the power of the (antique) 6800 core, and the 68HC05 family16 had a severely reduced core by lower price. Actually 4-bit MCUs outsold all other kinds of processor until the early 1990s and 8-bit MCUs, now the most popular, are likely to continue in this role for the foreseeable future.

All these MPUs and MCUs were based on the von Neumann architecture (see Fig. 3.1 on page 42) used by mainframe computers. The alternative Harvard architecture (see Fig. 3.2 on page 44), which is chiefly distinguished by having a separate memory space for program and data, originated at Harvard university for a US Defence department computing project, but was rejected in favor of a rival von Neumann design from Princeton university. The first MPU using this architecture was the Signetics 8X300, and this was adapted by General Instruments in the mid 1970s for use as a Peripheral Interface Controller (PIC) which was designed to be a programmable I/O port for their 16-bit CP1600 MPU.

16The 68HC05 has found a niche as the computing engine of smart cards, where highpower computing is not a priority.

4. The PIC16F84 Microcontroller 85

Fig. 4.2 Architecture of the PIC16F84 microcontroller

store address space. That is the various ports appear to the software to be in the Data store. In more detail we have:

Central Processor Unit

As a consequence of the Harvard architecture, the CPU is split between the fetch and execution function, both of which operate in parallel with a minimum of interaction.

Fetch

The fetch section comprises a 13-bit Program Counter (PC) addressing the Program store via the Program address bus, and a two-deep Instruction pipeline through which 14-bit instructions via the Program data bus progress through to the Instruction decoder – see Fig. 3.3 on page 45.

The Program Counter is actually located in the Data file store at location File 2 and is labelled as PCL (Program Counter Low byte) in Fig. 4.6.

86 The Quintessential PIC Microcontroller

This means that it can be accessed and manipulated by the software in the same manner as any other file register. For example, if the contents of the Working register were n, then the instruction addwf 2,f (see page 49) overwrites File 2 (i.e. the PC) with its original value plus n – that is skip forward n places. A practical example is given in Program 6.4 on page 149.

There is one problem with this example, which arises because the PC is actually 13-bits wide and File 2 only holds the lower eight bits, PC[7…0]. The upper five bits, PC[12…8] are held in a ‘buried’ register; that is not directly accessible to the programmer. Actually any instruction that directly writes to File 2, such as our example above, does change all 13 PC bits as shown in Fig. 4.3. Not only will the 8-bit outcome of the instruction addwf 2,f be placed in the lower byte of the PC but the lower five bits of the PC bu er register at File 0Ah, labelled PCLATH (for Program Counter LATch High byte) in Fig. 4.3, are automatically copied into the high byte of the Program Counter. The PCLATH file data register is cleared when the PIC is reset and so an instruction like our example will usually result in an address in the first 256-byte ‘page’ of program memory unless PLATH is loaded with a non-zero value. Thus care needs to be taken when altering the state of the PC by writing to PCL in this manner; especially if the outcome overflows its 8-bit field. Instructions that indirectly alter the value of the PC, such as goto, will also use part of the contents of PCLATH in updating the PC. Such instructions carry an 11-bit address as part of the instruction code. Here bits PCLATH[4:3] are moved over to the corresponding PC bits 12 & 11 to give a complete 13-bit PC update

– see Fig. 5.4 on page 114.

Associated with the Program Counter is an area of buried storage that can stack up to eight copies of the PC. The current value of the PC is pushed into this stack when a subroutine is called or an interrupt is serviced. Conversely a return from a subroutine or interrupt causes the

File 0Ah

Fig. 4.3 Showing how all 13 bits of the Program Counter are altered when writing to PCL.

4. The PIC16F84 Microcontroller 87

last stacked PC value to be popped out again into the PC. Details are given in Chapters 6 and 7.

The PIC microcontrollers have an integral oscillator that generates the internal timing sequences. The oscillator frequency fosc is normally controlled by an external crystal (or ceramic)-capacitor network across the device OSC1 and OSC2 pins – see Fig. 10.4 on page 258. A resistorcapacitor connected to OSC1 may be used as the timing elements where lower precision and frequency stability is not an issue. In this case OSC2/CLKOUT outputs a signal of frequency 14 × fosc. Alternatively an external oscillator can be used as the master clock into OSC1/CLKIN. The

PIC16F84 has a maximum frequency fOSC of 10 MHz but there is no minimum. As we shall see (Fig. 10.2 on page 256) the lower the frequency

the smaller is the power consumption. Unless otherwise stated, we will assume a fosc of 4 MHz for the rest of the text.

The internal oscillator/clock circuitry must be configured to the appropriate mode, as described in Fig. 10.5 on page 261. This is normally done when code is blasted into the Program store flash EEPROM. When the PIC is powered up (external supply voltage is applied) a 72 ms internal reset pulse is generated by the Power-up timer after the supply rises above approximately 2 volts, followed by 1024 clock pulses, counted by the Oscillator Start-Up timer to ensure that the internal oscillator has stabilised. This latter guard timer only operates for crystal-type oscillator modes – see Table 86 on page 258. The Power-Up timer does not operate if an external reset is applied to the Master CLeaR (MCLR) pin.

fosc

Q1

Q2

Q3

Q4

Fig. 4.4 Internal clock sequencing waveforms.

4. The PIC16F84 Microcontroller 89

12 − 24 = 88B0. C also functions as an input/output bit for the Rotate instructions, as shown in Fig. 3.7 on page 61.

The label R/W ? in Fig. 4.5 indicates that this bit can be read from or written to and has an indeterminate value on a power-up reset – its value does not alter on any other type of reset.

Digit Carry flag

Bit 1 of the Status register is the DC flag. This operates in the same manner as the standard C flag but holds the Carry out from the lower nybble to the upper nybble; that is from bit 3 to bit 4. In the same manner DC holds the complement of the Borrow out from bit 3 to bit 4. Knowledge of the Carry activity between the lower and upper halves of the byte is useful where binary coded decimal data is being manipulated. Here each nybble holds a 4-bit representation of the decimal digits 0…9 (see page 6) and the half carry then indicates carries between decimal decades.

Zero flag

Bit 2 of the Status register is the Z flag. This is set whenever the outcome of the instruction is zero, otherwise it is cleared.

Status register (SR) File 3

Power Down

By sleep instruction 0

By clrwdt instruction 1

Fig. 4.5 The PIC16F84 Status register

Unlike most MCUs, there are no instructions to specifically clear or set a flag, such as sec for SEt Carry.17 However, as the Status register is accessible as a file in the Data store, then any instruction that can alter the contents of a file can potentially change the state of a flag. There is a potential problem in that many of these instructions a ect one or

17For example the Motorola 6800/5/11 families.