Файл: The quintessential PIC microcontroller (S. Katzen, 2000).pdf

12. One Bit at a Time 307

SCK

RA1

RA0 SDO

Fig. 12.2 Serial interface to a 3-digit 7-segment display.

driver routine of Program 11.7 on page 301 which converts a binary byte to an array of BCD digits in HUNDREDS, TENS and UNITS. These are mapped to 7-segment code and then sent out to each digit 8-bits at a time.

To serialize this process we require to design a subroutine to put each bit of a specified file register DATA_OUT out at SDO while pulsing SCK, beginning with the leftmost bit. A task list for such a subroutine is:

1.Bring SCK low.

2.COUNT = 8.

3.WHILE COUNT > 0 DO:

(a)Shift DATA_OUT left into Carry.

(b)Copy Carry to SDO.

(c) Pulse SCK / \ .

(d) Decrement COUNT.

Program 12.1 shows two subroutines. The first called DISPLAY is closely akin to Program 11.7 in that it calls the subroutines BIN_2_BCD and then sends the 7-segment coded bytes out to the interface registers. In this instance the units byte is sent first as this will eventually be shifted to the far end of the chain; followed by the tens and finally the hundreds byte.

The actual serial transmission is handled by the subroutine SPI_WRITE, which implements our task list. The datum placed by the caller in file register DATA_OUT is shifted left and the state of the Carry bit used to make the Serial Data Out pin RA0 0 or 1. The Serial ClocK pin RA1 is then toggled once / \ to shift the data into the shift register chain. This is repeated eight times to complete the transaction, which takes a maxi-

12. One Bit at a Time 309

Where a long chain of shift registers is being serviced, speed may be improved a little if each register has its own data feed but all clocked with the same SCK pin or sharing the same lines but each with a separate Enable. This latter technique is the method used in Fig. 12.8.

One problem with our shift register technique is that for the period where shifting is in process the data appearing at the port outputs are not valid; for 23 clock pulses in our example. Of course in this situation the response of the eye to microsecond changes in illumination makes this observation spurious. However, this may not always be the case and in such instances the shift register may be bu ered from the parallel outputs using an array of D flip flops or latches, which can be loaded after the shifting process has been completed to give a single update.

Fig. 12.3 Logic functional diagram of the 74HCT595 octal shift register with output register.

Rather than employing a separate bu er register, a more e cient solution typically uses the 74HCT595 of Fig. 12.3 with its integral 8-bit parallel-in parallel-out (PIPO) register between the shift register and the outside world. A rising edge / on the RCK (Register ClocK) pin transfers the serialized data to the parallel outputs. The last stage output of the shift register is made available to allow cascading to any length. All RCK pins can be pulsed together to allow the entire chain to simultaneously update.

One example where rippling of data may be undesirable, is were a digital datum is to be converted to its analog equivalent. In Fig. 12.4 the conversion is carried out using a National Semiconductor DAC0800. Essentially the analog voltage is a linear function of the 8-bit digital input