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Приложение
// Device: Altera EP3C10E144C8 Package TQFP144
// This file contains Slow Corner delays for the design using part EP3C10E144C8,
// with speed grade 8, core voltage 1.2V, and temperature 0 Celsius
// This SDF file should be used for ModelSim-Altera (VHDL) only
(DELAYFILE
(SDFVERSION "2.1")
(DESIGN "vga")
(DATE "10/17/2014 14:12:04")
(VENDOR "Altera")
(PROGRAM "Quartus II 64-Bit")
(VERSION "Version 13.0.0 Build 156 04/24/2013 SJ Web Edition")
(DIVIDER .)
(TIMESCALE 1 ps)
(CELL
(CELLTYPE "cycloneiii_ram_register")
(INSTANCE \\inst3\|altsyncram_component\|auto_generated\|ram_block1a1\\.addr_a_register)
(DELAY
(ABSOLUTE
(PORT d[0] (2112:2112:2112) (1918:1918:1918))
(PORT d[1] (1704:1704:1704) (1536:1536:1536))
(PORT d[2] (1719:1719:1719) (1560:1560:1560))
(PORT d[3] (1643:1643:1643) (1498:1498:1498))
(PORT d[4] (1965:1965:1965) (1748:1748:1748))
(PORT d[5] (1617:1617:1617) (1423:1423:1423))
(PORT d[6] (2008:2008:2008) (1763:1763:1763))
(PORT d[7] (1621:1621:1621) (1431:1431:1431))
(PORT d[8] (1627:1627:1627) (1422:1422:1422))
(PORT d[9] (2021:2021:2021) (1755:1755:1755))
(PORT d[10] (1653:1653:1653) (1452:1452:1452))
(PORT d[11] (1624:1624:1624) (1430:1430:1430))
(PORT clk (1818:1818:1818) (1879:1879:1879))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (230:230:230))
)
)
(CELL
(CELLTYPE "cycloneiii_ram_register")
(INSTANCE \\inst3\|altsyncram_component\|auto_generated\|ram_block1a1\\.active_core_port_a)
(DELAY
(ABSOLUTE
(PORT clk (1818:1818:1818) (1879:1879:1879))
)
)
)
(CELL
(CELLTYPE "cycloneiii_ram_pulse_generator")
(INSTANCE \\inst3\|altsyncram_component\|auto_generated\|ram_block1a1\\.rpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1819:1819:1819) (1880:1880:1880))
(IOPATH (posedge clk) pulse (0:0:0) (2853:2853:2853))
)
)
)
(CELL
(CELLTYPE "cycloneiii_ram_register")
(INSTANCE \\inst3\|altsyncram_component\|auto_generated\|ram_block1a1\\.dataout_a_register)
(DELAY
(ABSOLUTE
(PORT clk (1773:1773:1773) (1832:1832:1832))
(IOPATH (posedge clk) q (355:355:355) (355:355:355))
)
)
(TIMINGCHECK
(SETUP d (posedge clk) (56:56:56))
(HOLD d (posedge clk) (190:190:190))
)
)
(CELL
(CELLTYPE "cycloneiii_ram_register")
(INSTANCE \\inst3\|altsyncram_component\|auto_generated\|ram_block1a1\\.active_core_port_b)
(DELAY
(ABSOLUTE
(PORT clk (845:845:845) (866:866:866))
)
)
)
(CELL
(CELLTYPE "cycloneiii_ram_pulse_generator")
(INSTANCE \\inst3\|altsyncram_component\|auto_generated\|ram_block1a1\\.rpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (846:846:846) (867:867:867))
)
)
)
(CELL
(CELLTYPE "cycloneiii_ram_pulse_generator")
(INSTANCE \\inst3\|altsyncram_component\|auto_generated\|ram_block1a1\\.ftpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (846:846:846) (867:867:867))
(IOPATH (posedge clk) pulse (0:0:0) (3162:3162:3162))
)
)
)
(CELL
(CELLTYPE "cycloneiii_ram_pulse_generator")
(INSTANCE \\inst3\|altsyncram_component\|auto_generated\|ram_block1a1\\.rwpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (846:846:846) (867:867:867))
(IOPATH (posedge clk) pulse (0:0:0) (3162:3162:3162))
)
)
)
(CELL
(CELLTYPE "cycloneiii_ram_register")
(INSTANCE \\inst3\|altsyncram_component\|auto_generated\|ram_block1a0\\.addr_a_register)
(DELAY
(ABSOLUTE
(PORT d[0] (1580:1580:1580) (1407:1407:1407))
(PORT d[1] (1622:1622:1622) (1429:1429:1429))
(PORT d[2] (1625:1625:1625) (1443:1443:1443))
(PORT d[3] (2669:2669:2669) (2297:2297:2297))
(PORT d[4] (1405:1405:1405) (1289:1289:1289))
(PORT d[5] (1662:1662:1662) (1502:1502:1502))
(PORT d[6] (1645:1645:1645) (1458:1458:1458))
(PORT d[7] (1340:1340:1340) (1239:1239:1239))
(PORT d[8] (1634:1634:1634) (1487:1487:1487))
(PORT d[9] (1367:1367:1367) (1260:1260:1260))
(PORT d[10] (1661:1661:1661) (1501:1501:1501))
(PORT d[11] (1892:1892:1892) (1626:1626:1626))
(PORT clk (1811:1811:1811) (1877:1877:1877))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (230:230:230))
)
)
(CELL
(CELLTYPE "cycloneiii_ram_register")
(INSTANCE \\inst3\|altsyncram_component\|auto_generated\|ram_block1a0\\.active_core_port_a)
(DELAY
(ABSOLUTE
(PORT clk (1811:1811:1811) (1877:1877:1877))
)
)
)
(CELL
(CELLTYPE "cycloneiii_ram_pulse_generator")
(INSTANCE \\inst3\|altsyncram_component\|auto_generated\|ram_block1a0\\.rpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1812:1812:1812) (1878:1878:1878))
(IOPATH (posedge clk) pulse (0:0:0) (2853:2853:2853))
)
)
)
(CELL
(CELLTYPE "cycloneiii_ram_register")
(INSTANCE \\inst3\|altsyncram_component\|auto_generated\|ram_block1a0\\.dataout_a_register)
(DELAY
(ABSOLUTE
(PORT clk (1766:1766:1766) (1830:1830:1830))
(IOPATH (posedg
(INSTANCE \\inst3\|altsyncram_component\|auto_generated\|ram_block1a4\\.rpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (858:858:858) (881:881:881))
)
)
)
(CELL
(CELLTYPE "cycloneiii_ram_pulse_generator")
(INSTANCE \\inst3\|altsyncram_component\|auto_generated\|ram_block1a4\\.ftpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (858:858:858) (881:881:881))
(IOPATH (posedge clk) pulse (0:0:0) (3162:3162:3162))
)
)
)
(CELL
(CELLTYPE "cycloneiii_ram_pulse_generator")
(INSTANCE \\inst3\|altsyncram_component\|auto_generated\|ram_block1a4\\.rwpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (858:858:858) (881:881:881))
(IOPATH (posedge clk) pulse (0:0:0) (3162:3162:3162))
)
)
)
(CELL
(CELLTYPE "cycloneiii_ram_register")
(INSTANCE \\inst4\|altsyncram_component\|auto_generated\|ram_block1a24\\.datain_a_register)
(DELAY
(ABSOLUTE
(PORT d[0] (1692:1692:1692) (1540:1540:1540))
(PORT d[1] (1687:1687:1687) (1540:1540:1540))
(PORT d[2] (1681:1681:1681) (1542:1542:1542))
(PORT d[3] (1745:1745:1745) (1595:1595:1595))
(PORT clk (1821:1821:1821) (1886:1886:1886))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (230:230:230))
)
)
(CELL
(CELLTYPE "cycloneiii_ram_register")
(INSTANCE \\inst4\|altsyncram_component\|auto_generated\|ram_block1a24\\.addr_a_register)
(DELAY
(ABSOLUTE
(PORT d[0] (1323:1323:1323) (1236:1236:1236))
(PORT d[1] (1910:1910:1910) (1684:1684:1684))
(PORT d[2] (2032:2032:2032) (1781:1781:1781))
(PORT d[3] (2051:2051:2051) (1822:1822:1822))
(PORT d[4] (2604:2604:2604) (2236:2236:2236))
(PORT d[5] (2650:2650:2650) (2299:2299:2299))
(PORT d[6] (2242:2242:2242) (1967:1967:1967))
(PORT d[7] (2303:2303:2303) (2045:2045:2045))
(PORT d[8] (2634:2634:2634) (2244:2244:2244))
(PORT d[9] (2682:2682:2682) (2316:2316:2316))
(PORT d[10] (2314:2314:2314) (1959:1959:1959))
(PORT clk (1818:1818:1818) (1882:1882:1882))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (230:230:230))
)
)
(CELL
(CELLTYPE "cycloneiii_ram_register")
(INSTANCE \\inst4\|altsyncram_component\|auto_generated\|ram_block1a24\\.we_a_register)
(DELAY
(ABSOLUTE
(PORT d[0] (1534:1534:1534) (1348:1348:1348))
(PORT clk (1818:1818:1818) (1882:1882:1882))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (230:230:230))
)
)
(CELL
(CELLTYPE "cycloneiii_ram_register")
(INSTANCE \\inst4\|altsyncram_component\|auto_generated\|ram_block1a24\\.active_core_port_a)
(DELAY
(ABSOLUTE
(PORT clk (1821:1821:1821) (1886:1886:1886))
(PORT d[0] (2156:2156:2156) (1980:1980:1980))
)
)
)
(CELL
(CELLTYPE "cycloneiii_ram_pulse_generator")
(INSTANCE \\inst4\|altsyncram_component\|auto_generated\|ram_block1a24\\.wpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1822:1822:1822) (1887:1887:1887))
(IOPATH (posedge clk) pulse (0:0:0) (2490:2490:2490))
)
)
)
(CELL
(CELLTYPE "cycloneiii_ram_pulse_generator")
(INSTANCE \\inst4\|altsyncram_component\|auto_generated\|ram_block1a24\\.rpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1822:1822:1822) (1887:1887:1887))
)
)
)
(CELL
(CELLTYPE "cycloneiii_ram_pulse_generator")
(INSTANCE \\inst4\|altsyncram_component\|auto_generated\|ram_block1a24\\.ftpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1822:1822:1822) (1887:1887:1887))
(IOPATH (posedge clk) pulse (0:0:0) (3129:3129:3129))
)
)
)
(CELL
(CELLTYPE "cycloneiii_ram_pulse_generator")
(INSTANCE \\inst4\|altsyncram_component\|auto_generated\|ram_block1a24\\.rwpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1822:1822:1822) (1887:1887:1887))
(IOPATH (posedge clk) pulse (0:0:0) (3129:3129:3129))
)
)
)
(CELL
(CELLTYPE "cycloneiii_ram_register")
(INSTANCE \\inst4\|altsyncram_component\|auto_generated\|ram_block1a24\\.addr_b_register)
(DELAY
(ABSOLUTE
(PORT d[0] (1542:1542:1542) (1377:1377:1377))
(PORT d[1] (2606:2606:2606) (2234:2234:2234))
(PORT d[2] (1979:1979:1979) (1745:1745:1745))
(PORT d[3] (2612:2612:2612) (2215:2215:2215))
(PORT d[4] (2498:2498:2498) (2146:2146:2146))
(PORT d[5] (2267:2267:2267) (1966:1966:1966))
(PORT d[6] (1692:1692:1692) (1516:1516:1516))
(PORT d[7] (2203:2203:2203) (1885:1885:1885))
(PORT d[8] (2067:2067:2067) (1827:1827:1827))
(PORT d[9] (2143:2143:2143) (1932:1932:1932))
(PORT d[10] (1762:1762:1762) (1590:1590:1590))
(PORT clk (1777:1777:1777) (1797:1797:1797))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (230:230:230))
)
)
(CELL
(CELLTYPE "cycloneiii_ram_register")
(INSTANCE \\inst4\|altsyncram_component\|auto_generated\|ram_block1a24\\.active_core_port_b)
(DELAY
(ABSOLUTE
(PORT clk (1777:1777:1777) (1797:1797:1797))
(PORT d[0] (1487:1487:1487) (1271:1271:1271))
)
)
)
(CELL
(CELLTYPE "cycloneiii_ram_pulse_generator")
(INSTANCE \\inst4\|altsyncram_component\|auto_generated\|ram_block1a24\\.rpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (1778:1778:1778) (1798:1798:1798))
(IOPATH (posedge clk) pulse (0:0:0) (2891:2891:2891))
)
)
)
(CELL
(CELLTYPE "cycloneiii_ram_pulse_generator")
(INSTANCE \\inst4\|altsyncram_component\|auto_generated\|ram_block1a24\\.ftpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (1778:1778:1778) (1798:1798:1798))
(IOPATH (posedge clk) pulse (0:0:0) (3162:3162:3162))
)
)
)
(CELL
(CELLTYPE "cycloneiii_ram_pulse_generator")
(INSTANCE \\inst4\|altsyncram_component\|auto_generated\|ram_block1a24\\.rwpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (1778:1778:1778) (1798:1798:1798))
(IOPATH (posedge clk) pulse (0:0:0) (3162:3162:3162))
)
)
)
(CELL
(CELLTYPE "cycloneiii_ram_register")
(INSTANCE \\inst4\|altsyncram_component\|auto_generated\|ram_block1a24\\.dataout_b_register)
(DELAY
(ABSOLUTE
(PORT clk (1768:1768:1768) (1790:1790:1790))
(IOPATH (posedge clk) q (353:353:353) (353:353:353))
)
)
(TIMINGCHECK
(SETUP d (posedge clk) (56:56:56))
(HOLD d (posedge clk) (190:190:190))
)
)
(CELL
(CELLTYPE "cycloneiii_ram_register")
(INSTANCE \\inst4\|altsyncram_component\|auto_generated\|ram_block1a8\\.datain_a_register)
(DELAY
(ABSOLUTE
(PORT d[0] (2437:2437:2437) (2103:2103:2103))
(PORT clk (1833:1833:1833) (1897:1897:1897))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (230:230:230))
)
)
(CELL
(CELLTYPE "cycloneiii_ram_register")
(INSTANCE \\inst4\|altsyncram_component\|auto_generated\|ram_block1a8\\.addr_a_register)
(DELAY
(ABSOLUTE
(PORT d[0] (2471:2471:2471) (2194:2194:2194))
(PORT d[1] (2219:2219:2219) (2061:2061:2061))
(PORT d[2] (2867:2867:2867) (2567:2567:2567))
(PORT d[3] (2443:2443:2443) (2206:2206:2206))
(PORT d[4] (2441:2441:2441) (2220:2220:2220))
(PORT d[5] (1442:1442:1442) (1347:1347:1347))
(PORT d[6] (1369:1369:1369) (1289:1289:1289))
(PORT d[7] (2069:2069:2069) (1909:1909:1909))
(PORT d[8] (2048:2048:2048) (1828:1828:1828))
(PORT d[9] (1795:1795:1795) (1668:1668:1668))
(PORT d[10] (2676:2676:2676) (2289:2289:2289))
(PORT d[11] (1969:1969:1969) (1721:1721:1721))
(PORT d[12] (2743:2743:2743) (2399:2399:2399))
(PORT clk (1830:1830:1830) (1893:1893:1893))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (230:230:230))
)
)
(CELL
(CELLTYPE "cycloneiii_ram_register")
(INSTANCE \\inst4\|altsyncram_component\|auto_generated\|ram_block1a8\\.we_a_register)
(DELAY
(ABSOLUTE
(PORT d[0] (2239:2239:2239) (1889:1889:1889))
(PORT clk (1830:1830:1830) (1893:1893:1893))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (230:230:230))
)
)
(CELL
(CELLTYPE "cycloneiii_ram_register")
(INSTANCE \\inst4\|altsyncram_component\|auto_generated\|ram_block1a8\\.active_core_port_a)
(DELAY
(ABSOLUTE
(PORT clk (1833:1833:1833) (1897:1897:1897))
(PORT d[0] (2861:2861:2861) (2521:2521:2521))
)
)
)
(CELL
(CELLTYPE "cycloneiii_ram_pulse_generator")
(INSTANCE \\inst4\|altsyncram_component\|auto_generated\|ram_block1a8\\.wpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1834:1834:1834) (1898:1898:1898))
(IOPATH (posedge clk) pulse (0:0:0) (2490:2490:2490))
)
)
)
(CELL
(CELLTYPE "cycloneiii_ram_pulse_generator")
(INSTANCE \\inst4\|altsyncram_component\|auto_generated\|ram_block1a8\\.rpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1834:1834:1834) (1898:1898:1898))
)
)
)
(CELL
(CELLTYPE "cycloneiii_ram_pulse_generator")
(INSTANCE \\inst4\|altsyncram_component\|auto_generated\|ram_block1a8\\.ftpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1834:1834:1834) (1898:1898:1898))
(IOPATH (posedge clk) pulse (0:0:0) (3129:3129:3129))
)
)
)
(CELL
(CELLTYPE "cycloneiii_ram_pulse_generator")
(INSTANCE \\inst4\|altsyncram_component\|auto_generated\|ram_block1a8\\.rwpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1834:1834:1834) (1898:1898:1898))
(IOPATH (posedge clk) pulse (0:0:0) (3129:3129:3129))
)
)
)
(CELL
(CELLTYPE "cycloneiii_ram_register")
(INSTANCE \\inst4\|altsyncram_component\|auto_generated\|ram_block1a8\\.addr_b_register)
(DELAY
(ABSOLUTE
(PORT d[0] (1649:1649:1649) (1506:1506:1506))
(PORT d[1] (2345:2345:2345) (2087:2087:2087))
(PORT d[2] (2438:2438:2438) (2210:2210:2210))
(PORT d[3] (1730:1730:1730) (1566:1566:1566))
(PORT d[4] (2477:2477:2477) (2248:2248:2248))
(PORT d[5] (1641:1641:1641) (1477:1477:1477))
(PORT d[6] (2456:2456:2456) (2173:2173:2173))
(PORT d[7] (2252:2252:2252) (1977:1977:1977))
(PORT d[8] (2015:2015:2015) (1778:1778:1778))
(PORT d[9] (1659:1659:1659) (1513:1513:1513))
(PORT d[10] (1677:1677:1677) (1528:1528:1528))
(PORT d[11] (1602:1602:1602) (1433:1433:1433))
(PORT d[12] (2310:2310:2310) (2082:2082:2082))
(PORT clk (1789:1789:1789) (1808:1808:1808))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (230:230:230))
)
)
(CELL
(CELLTYPE "cycloneiii_ram_register")
(INSTANCE \\inst4\|altsyncram_component\|auto_generated\|ram_block1a8\\.active_core_port_b)
(DELAY
(ABSOLUTE
(PORT clk (1789:1789:1789) (1808:1808:1808))
(PORT d[0] (2175:2175:2175) (2534:2534:2534))
)
)
)
(CELL
(CELLTYPE "cycloneiii_ram_pulse_generator")
(INSTANCE \\inst4\|altsyncram_component\|auto_generated\|ram_block1a8\\.rpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (1790:1790:1790) (1809:1809:1809))
(IOPATH (posedge clk) pulse (0:0:0) (2891:2891:2891))
)
)
)
(CELL
(CELLTYPE "cycloneiii_ram_pulse_generator")
(INSTANCE \\inst4\|altsyncram_component\|auto_generated\|ram_block1a8\\.ftpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (1790:1790:1790) (1809:1809:1809))
(IOPATH (posedge clk) pulse (0:0:0) (3162:3162:3162))
)
)
)
(CELL
(CELLTYPE "cycloneiii_ram_pulse_generator")
(INSTANCE \\inst4\|altsyncram_component\|auto_generated\|ram_block1a8\\.rwpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (1790:1790:1790) (1809:1809:1809))
(IOPATH (posedge clk) pulse (0:0:0) (3162:3162:3162))
)
)
)
(CELL
(CELLTYPE "cycloneiii_ram_register")
(INSTANCE \\inst4\|altsyncram_component\|auto_generated\|ram_block1a8\\.dataout_b_register)
(DELAY
(ABSOLUTE
(PORT clk (1780:1780:1780) (1801:1801:1801))
(IOPATH (posedge clk) q (353:353:353) (353:353:353))
)
)
(TIMINGCHECK
(SETUP d (posedge clk) (56:56:56))
(HOLD d (posedge clk) (190:190:190))
)
)
(CELL
(CELLTYPE "cycloneiii_ram_register")
(INSTANCE \\inst4\|altsyncram_component\|auto_generated\|ram_block1a11\\.datain_a_register)
(DELAY
(ABSOLUTE
(PORT d[0] (1296:1296:1296) (1217:1217:1217))
(PORT clk (1819:1819:1819) (1884:1884:1884))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (230:230:230))
)
)
(CELL
(CELLTYPE "cycloneiii_ram_register")
(INSTANCE \\inst4\|altsyncram_component\|auto_generated\|ram_block1a11\\.addr_a_register)