Файл: Проектирование устройства формирования тестового видеоизображения на базе плис.doc
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(DELAY
(ABSOLUTE
(PORT d[0] (1585:1585:1585) (1379:1379:1379))
(PORT d[1] (2164:2164:2164) (1881:1881:1881))
(PORT d[2] (3105:3105:3105) (2712:2712:2712))
(PORT d[3] (2773:2773:2773) (2486:2486:2486))
(PORT d[4] (2028:2028:2028) (1822:1822:1822))
(PORT d[5] (3019:3019:3019) (2615:2615:2615))
(PORT d[6] (3068:3068:3068) (2704:2704:2704))
(PORT d[7] (3104:3104:3104) (2743:2743:2743))
(PORT d[8] (3421:3421:3421) (2974:2974:2974))
(PORT d[9] (2709:2709:2709) (2390:2390:2390))
(PORT d[10] (3135:3135:3135) (2695:2695:2695))
(PORT d[11] (2099:2099:2099) (1925:1925:1925))
(PORT d[12] (3070:3070:3070) (2691:2691:2691))
(PORT clk (1816:1816:1816) (1880:1880:1880))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (230:230:230))
)
)
(CELL
(CELLTYPE "cycloneiii_ram_register")
(INSTANCE \\inst4\|altsyncram_component\|auto_generated\|ram_block1a11\\.we_a_register)
(DELAY
(ABSOLUTE
(PORT d[0] (1515:1515:1515) (1310:1310:1310))
(PORT clk (1816:1816:1816) (1880:1880:1880))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (230:230:230))
)
)
(CELL
(CELLTYPE "cycloneiii_ram_register")
(INSTANCE \\inst4\|altsyncram_component\|auto_generated\|ram_block1a11\\.active_core_port_a)
(DELAY
(ABSOLUTE
(PORT clk (1819:1819:1819) (1884:1884:1884))
(PORT d[0] (2137:2137:2137) (1942:1942:1942))
)
)
)
(CELL
(CELLTYPE "cycloneiii_ram_pulse_generator")
(INSTANCE \\inst4\|altsyncram_component\|auto_generated\|ram_block1a11\\.wpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1820:1820:1820) (1885:1885:1885))
(IOPATH (posedge clk) pulse (0:0:0) (2490:2490:2490))
)
)
)
(CELL
(CELLTYPE "cycloneiii_ram_pulse_generator")
(INSTANCE \\inst4\|altsyncram_component\|auto_generated\|ram_block1a11\\.rpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1820:1820:1820) (1885:1885:1885))
)
)
)
(CELL
(CELLTYPE "cycloneiii_ram_pulse_generator")
(INSTANCE \\inst4\|altsyncram_component\|auto_generated\|ram_block1a11\\.ftpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1820:1820:1820) (1885:1885:1885))
(IOPATH (posedge clk) pulse (0:0:0) (3129:3129:3129))
)
)
)
(CELL
(CELLTYPE "cycloneiii_ram_pulse_generator")
(INSTANCE \\inst4\|altsyncram_component\|auto_generated\|ram_block1a11\\.rwpgen_a)
(DELAY
(ABSOLUTE
(PORT clk (1820:1820:1820) (1885:1885:1885))
(IOPATH (posedge clk) pulse (0:0:0) (3129:3129:3129))
)
)
)
(CELL
(CELLTYPE "cycloneiii_ram_register")
(INSTANCE \\inst4\|altsyncram_component\|auto_generated\|ram_block1a11\\.addr_b_register)
(DELAY
(ABSOLUTE
(PORT d[0] (2405:2405:2405) (2123:2123:2123))
(PORT d[1] (2559:2559:2559) (2244:2244:2244))
(PORT d[2] (1733:1733:1733) (1528:1528:1528))
(PORT d[3] (3367:3367:3367) (2869:2869:2869))
(PORT d[4] (1232:1232:1232) (1090:1090:1090))
(PORT d[5] (1785:1785:1785) (1648:1648:1648))
(PORT d[6] (2830:2830:2830) (2482:2482:2482))
(PORT d[7] (2593:2593:2593) (2274:2274:2274))
(PORT d[8] (2483:2483:2483) (2199:2199:2199))
(PORT d[9] (971:971:971) (906:906:906))
(PORT d[10] (968:968:968) (904:904:904))
(PORT d[11] (2539:2539:2539) (2332:2332:2332))
(PORT d[12] (2046:2046:2046) (1834:1834:1834))
(PORT clk (1775:1775:1775) (1795:1795:1795))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (230:230:230))
)
)
(CELL
(CELLTYPE "cycloneiii_ram_register")
(INSTANCE \\inst4\|altsyncram_component\|auto_generated\|ram_block1a11\\.active_core_port_b)
(DELAY
(ABSOLUTE
(PORT clk (1775:1775:1775) (1795:1795:1795))
(PORT d[0] (914:914:914) (1054:1054:1054))
)
)
)
(CELL
(CELLTYPE "cycloneiii_ram_pulse_generator")
(INSTANCE \\inst4\|altsyncram_component\|auto_generated\|ram_block1a11\\.rpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (1776:1776:1776) (1796:1796:1796))
(IOPATH (posedge clk) pulse (0:0:0) (2891:2891:2891))
)
)
)
(CELL
(CELLTYPE "cycloneiii_ram_pulse_generator")
(INSTANCE \\inst4\|altsyncram_component\|auto_generated\|ram_block1a11\\.ftpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (1776:1776:1776) (1796:1796:1796))
(IOPATH (posedge clk) pulse (0:0:0) (3162:3162:3162))
)
)
)
(CELL
(CELLTYPE "cycloneiii_ram_pulse_generator")
(INSTANCE \\inst4\|altsyncram_component\|auto_generated\|ram_block1a11\\.rwpgen_b)
(DELAY
(ABSOLUTE
(PORT clk (1776:1776:1776) (1796:1796:1796))
(IOPATH (posedge clk) pulse (0:0:0) (3162:3162:3162))
)
)
)
(CELL
(CELLTYPE "cycloneiii_ram_register")
(INSTANCE \\inst4\|altsyncram_component\|auto_generated\|ram_block1a11\\.dataout_b_register)
(DELAY
(ABSOLUTE
(PORT clk (1766:1766:1766) (1788:1788:1788))
(IOPATH (posedge clk) q (353:353:353) (353:353:353))
)
)
(TIMINGCHECK
(SETUP d (posedge clk) (56:56:56))
(HOLD d (posedge clk) (190:190:190))
)
)
(CELL
(CELLTYPE "cycloneiii_ram_register")
(INSTANCE \\inst4\|altsyncram_component\|auto_generated\|ram_block1a9\\.datain_a_register)
(DELAY
(ABSOLUTE
(PORT d[0] (2100:2100:2100) (1792:1792:1792))
(PORT clk (1835:1835:1835) (1899:1899:1899))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (230:230:230))
)
)
(CELL
(CELLTYPE "cycloneiii_ram_register")
(INSTANCE \\inst4\|altsyncram_component\|auto_generated\|ram_block1a9\\.addr_a_register)
(DELAY
(ABSOLUTE
(PORT d[0] (2035:2035:2035) (1795:1795:1795))
(PORT d[1] (2624:2624:2624) (2413:2413:2413))
(PORT d[2] (3224:3224:3224) (2927:2927:2927))
(PORT d[3] (2815:2815:2815) (2558:2558:2558))
(PORT d[4] (2820:2820:2820) (2567:2567:2567))
(PORT d[5] (1341:1341:1341) (1240:1240:1240))
(PORT d[6] (1721:1721:1721) (1619:1619:1619))
(PORT d[7] (1761:1761:1761) (1615:1615:1615))
(PORT d[8] (1729:1729:1729) (1535:1535:1535))
(PORT d[9] (1872:1872:1872) (1746:1746:1746))
(PORT d[10] (3048:3048:3048) (2625:2625:2625))
(PORT d[11] (2024:2024:2024) (1769:1769:1769))
(PORT d[12] (1629:1629:1629) (1457:1457:1457))
(PORT clk (1832:1832:1832) (1895:1895:1895))
)
)
(TIMINGCHECK
(HOLD d (posedge clk) (230:230:230))
)
)
(CELL
(CELLTYPE "cycloneiii_ram_register")
(INSTANCE \\inst4\|altsyncram_component\|auto_generated\|ram_block1a9\\.we_a_register)
(DELAY
(CELL
(CELLTYPE "cycloneiii_lcell_comb")
(INSTANCE \\inst\|red\[4\]\
3\\)(DELAY
(ABSOLUTE
(PORT datac (1530:1530:1530) (1428:1428:1428))
(PORT datad (226:226:226) (233:233:233))
(IOPATH datac combout (301:301:301) (285:285:285))
(IOPATH datad combout (167:167:167) (143:143:143))
)
)
)
)