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8-bit Timer/Counter2 with PWM and Asynchronous Operation

Timer/Counter2 is a general purpose, single channel, 8-bit Timer/Counter module. The main features are:

•Single Channel Counter

•Clear Timer on Compare Match (Auto Reload)

•Glitch-free, phase Correct Pulse Width Modulator (PWM)

•Frequency Generator

•10-bit Clock Prescaler

•Overflow and Compare Match Interrupt Sources (TOV2 and OCF2)

•Allows Clocking from External 32 kHz Watch Crystal Independent of the I/O Clock

Overview	A simplified block diagram of the 8-bit Timer/Counter is shown in Figure 45. For the
	actual placement of I/O pins, refer to “Pin Configurations” on page 2. CPU accessible
	I/O Registers, including I/O bits and I/O pins, are shown in bold. The device-specific I/O
	Register and bit locations are listed in the “8-bit Timer/Counter Register Description” on
	page 115.
	Figure 45. 8-bit Timer/Counter Block Diagram

TCCRn

count

clear

Control Logic

direction

clkTn

BOTTOM

TOP

Prescaler

Timer/Counter

TCNTn

= 0

= 0xFF

OCn

(Int. Req.)

Waveform

Generation

OCRn

DATA BUS

Synchronized Status Flags

Synchronization Unit

Status Flags

ASSRn

asynchronous Mode

Select (ASn)

TOVn

(Int. Req.)

TOSC1

T/C

Oscillator

TOSC2

clkI/O

OCn

clkI/O

clkASY

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Registers
	The Timer/Counter (TCNT2) and Output Compare Register (OCR2) are 8-bit registers.

	Interrupt request (shorten as Int.Req.) signals are all visible in the Timer Interrupt Flag
	Register (TIFR). All interrupts are individually masked with the Timer Interrupt Mask
	Register (TIMSK). TIFR and TIMSK are not shown in the figure since these registers are
	shared by other timer units.
	The Timer/Counter can be clocked internally, via the prescaler, or asynchronously
	clocked from the TOSC1/2 pins, as detailed later in this section. The asynchronous
	operation is controlled by the Asynchronous Status Register (ASSR). The Clock Select
	logic block controls which clock source the Timer/Counter uses to increment (or decre-
	ment) its value. The Timer/Counter is inactive when no clock source is selected. The
	output from the clock select logic is referred to as the timer clock (clkT2).
	The double buffered Output Compare Register (OCR2) is compared with the
	Timer/Counter value at all times. The result of the compare can be used by the wave-
	form generator to generate a PWM or variable frequency output on the Output Compare
	Pin (OC2). For details, see “Output Compare Unit” on page 105. The Compare Match
	event will also set the Compare Flag (OCF2) which can be used to generate an Output
	Compare interrupt request.
Definitions	Many register and bit references in this document are written in general form. A lower
	case “n” replaces the Timer/Counter number, in this case 2. However, when using the
	register or bit defines in a program, the precise form must be used (i.e., TCNT2 for
	accessing Timer/Counter2 counter value and so on).
	The definitions in Table 41 are also used extensively throughout the document.
	Table 41. Definitions

	BOTTOM	The counter reaches the BOTTOM when it becomes zero (0x00).
	MAX	The counter reaches its MAXimum when it becomes 0xFF (decimal 255).
	TOP	The counter reaches the TOP when it becomes equal to the highest
		value in the count sequence. The TOP value can be assigned to be the
		fixed value 0xFF (MAX) or the value stored in the OCR2 Register. The
		assignment is dependent on the mode of operation.

Timer/Counter Clock

Sources

The Timer/Counter can be clocked by an internal synchronous or an external asynchro-

nous clock source. The clock source clkT2 is by default equal to the MCU clock, clkI/O. When the AS2 bit in the ASSR Register is written to logic one, the clock source is taken

from the Timer/Counter Oscillator connected to TOSC1 and TOSC2. For details on asynchronous operation, see “Asynchronous Status Register – ASSR” on page 117. For details on clock sources and prescaler, see “Timer/Counter Prescaler” on page 121.

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Counter Unit

The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit. Figure 46 shows a block diagram of the counter and its surrounding environment.

Figure 46. Counter Unit Block Diagram

TOVn

DATA BUS

(Int. Req.)

count

clk Tn

T/C

TOSC1

clear

TCNTn

Control Logic

Prescaler

Oscillator

direction

TOSC2

BOTTOM

TOP

clkI/O

Signal description (internal signals):

count	Increment or decrement TCNT2 by 1.
direction	Selects between increment and decrement.
clear	Clear TCNT2 (set all bits to zero).
clkT2	Timer/Counter clock.
TOP	Signalizes that TCNT2 has reached maximum value.
BOTTOM	Signalizes that TCNT2 has reached minimum value (zero).

Depending on the mode of operation used, the counter is cleared, incremented, or decremented at each timer clock (clkT2). clkT2 can be generated from an external or internal clock source, selected by the clock select bits (CS22:0). When no clock source is selected (CS22:0 = 0) the timer is stopped. However, the TCNT2 value can be accessed by the CPU, regardless of whether clkT2 is present or not. A CPU write overrides (has priority over) all counter clear or count operations.

The counting sequence is determined by the setting of the WGM21 and WGM20 bits located in the Timer/Counter Control Register (TCCR2). There are close connections between how the counter behaves (counts) and how waveforms are generated on the Output Compare Output OC2. For more details about advanced counting sequences and waveform generation, see “Modes of Operation” on page 108.

The Timer/Counter Overflow (TOV2) Flag is set according to the mode of operation selected by the WGM21:0 bits. TOV2 can be used for generating a CPU interrupt.

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Output Compare Unit

The 8-bit comparator continuously compares TCNT2 with the Output Compare Register (OCR2). Whenever TCNT2 equals OCR2, the comparator signals a match. A match will set the Output Compare Flag (OCF2) at the next timer clock cycle. If enabled (OCIE2 = 1), the Output Compare Flag generates an Output Compare interrupt. The OCF2 Flag is automatically cleared when the interrupt is executed. Alternatively, the OCF2 Flag can be cleared by software by writing a logical one to its I/O bit location. The waveform generator uses the match signal to generate an output according to operating mode set by the WGM21:0 bits and Compare Output mode (COM21:0) bits. The max and bottom signals are used by the waveform generator for handling the special cases of the extreme values in some modes of operation (see “Modes of Operation” on page 108).

Figure 47 shows a block diagram of the Output Compare unit.

Figure 47. Output Compare Unit, Block Diagram

DATA BUS

OCRn		TCNTn

= (8-bit Comparator )

OCFn (Int. Req.)

TOP
BOTTOM	Waveform Generator
BOTTOM			OCxy
FOCn





	WGMn1:0	COMn1:0

The OCR2 Register is double buffered when using any of the Pulse Width Modulation (PWM) modes. For the normal and Clear Timer on Compare (CTC) modes of operation, the double buffering is disabled. The double buffering synchronizes the update of the OCR2 Compare Register to either top or bottom of the counting sequence. The synchronization prevents the occurrence of odd-length, non-symmetrical PWM pulses, thereby making the output glitch-free.

The OCR2 Register access may seem complex, but this is not case. When the double buffering is enabled, the CPU has access to the OCR2 Buffer Register, and if double buffering is disabled the CPU will access the OCR2 directly.

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