Файл: ATmega8.pdf

Force Output Compare

In non-PWM Waveform Generation modes, the match output of the comparator can be

forced by writing a one to the Force Output Compare (FOC2) bit. Forcing Compare

Match will not set the OCF2 Flag or reload/clear the timer, but the OC2 pin will be

updated as if a real Compare Match had occurred (the COM21:0 bits settings define

whether the OC2 pin is set, cleared or toggled).

Compare Match Blocking by

All CPU write operations to the TCNT2 Register will block any Compare Match that

TCNT2 Write

occurs in the next timer clock cycle, even when the timer is stopped. This feature allows

OCR2 to be initialized to the same value as TCNT2 without triggering an interrupt when

the Timer/Counter clock is enabled.

Using the Output Compare

Since writing TCNT2 in any mode of operation will block all compare matches for one

Unit

timer clock cycle, there are risks involved when changing TCNT2 when using the Output

Compare channel, independently of whether the Timer/Counter is running or not. If the

value written to TCNT2 equals the OCR2 value, the Compare Match will be missed,

resulting in incorrect waveform generation. Similarly, do not write the TCNT2 value

equal to BOTTOM when the counter is downcounting.

The setup of the OC2 should be performed before setting the Data Direction Register for

the port pin to output. The easiest way of setting the OC2 value is to use the Force Out-

put Compare (FOC2) strobe bit in Normal mode. The OC2 Register keeps its value even

when changing between waveform generation modes.

Be aware that the COM21:0 bits are not double buffered together with the compare

value. Changing the COM21:0 bits will take effect immediately.

Compare Output Mode and

The Waveform Generator uses the COM21:0 bits differently in normal, CTC, and PWM

Waveform Generation

modes. For all modes, setting the COM21:0 = 0 tells the waveform generator that no

action on the OC2 Register is to be performed on the next Compare Match. For com-

pare output actions in the non-PWM modes refer to Table 43 on page 116. For fast

PWM mode, refer to Table 44 on page 116, and for phase correct PWM refer to Table

45 on page 116.

A change of the COM21:0 bits state will have effect at the first Compare Match after the

bits are written. For non-PWM modes, the action can be forced to have immediate effect

by using the FOC2 strobe bits.

Modes of Operation

The mode of operation (i.e., the behavior of the Timer/Counter and the Output Compare

pins) is defined by the combination of the Waveform Generation mode (WGM21:0) and

Compare Output mode (COM21:0) bits. The Compare Output mode bits do not affect

the counting sequence, while the Waveform Generation mode bits do. The COM21:0

bits control whether the PWM output generated should be inverted or not (inverted or

non-inverted PWM). For non-PWM modes the COM21:0 bits control whether the output

should be set, cleared, or toggled at a Compare Match (see “Compare Match Output

Unit” on page 107).

For detailed timing information refer to “Timer/Counter Timing Diagrams” on page 113.

Normal Mode

The simplest mode of operation is the Normal mode (WGM21:0 = 0). In this mode the

counting direction is always up (incrementing), and no counter clear is performed. The

counter simply overruns when it passes its maximum 8-bit value (TOP = 0xFF) and then

restarts from the bottom (0x00). In normal operation the Timer/Counter Overflow Flag

(TOV2) will be set in the same timer clock cycle as the TCNT2 becomes zero. The

TOV2 Flag in this case behaves like a ninth bit, except that it is only set, not cleared.

However, combined with the timer overflow interrupt that automatically clears the TOV2

Flag, the timer resolution can be increased by software. There are no special cases to

consider in the Normal mode, a new counter value can be written anytime.

The Output Compare unit can be used to generate interrupts at some given time. Using

the Output Compare to generate waveforms in Normal mode is not recommended,

since this will occupy too much of the CPU time.

ATmega8(L)

Clear Timer on Compare

In Clear Timer on Compare or CTC mode (WGM21:0 = 2), the OCR2 Register is used to

Match (CTC) Mode

manipulate the counter resolution. In CTC mode the counter is cleared to zero when the

counter value (TCNT2) matches the OCR2. The OCR2 defines the top value for the

counter, hence also its resolution. This mode allows greater control of the Compare

Match output frequency. It also simplifies the operation of counting external events.

The timing diagram for the CTC mode is shown in Figure 49. The counter value

(TCNT2) increases until a Compare Match occurs between TCNT2 and OCR2, and then

counter (TCNT2) is cleared.

Figure 49. CTC Mode, Timing Diagram

OCn Interrupt Flag Set

fOCn =

fclk_I/O

2--------N---------(--1-----+-----OCRn----------------)-