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Timer/Counter Register –
TCNT2
Output Compare Register –
OCR2
ATmega8(L)
• Bit 2:0 – CS22:0: Clock Select
The three clock select bits select the clock source to be used by the Timer/Counter, see Table 46.
Table 46. Clock Select Bit Description
CS22 |
CS21 |
CS20 |
Description |
||||||||
0 |
0 |
0 |
No clock source (Timer/Counter stopped). |
||||||||
0 |
0 |
1 |
clkT2S/(No prescaling) |
||||||||
0 |
1 |
0 |
clkT2S/8 (From prescaler) |
||||||||
0 |
1 |
1 |
clkT2S/32 (From prescaler) |
||||||||
1 |
0 |
0 |
clkT2S/64 (From prescaler) |
||||||||
1 |
0 |
1 |
clkT2S/128 (From prescaler) |
||||||||
1 |
1 |
0 |
clkT2S/256 (From prescaler) |
||||||||
1 |
1 |
1 |
clkT2S/1024 (From prescaler) |
||||||||
Bit |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|||
TCNT2[7:0] |
TCNT2 |
||||||||||
Read/Write |
R/W |
R/W |
R/W |
R/W |
R/W |
R/W |
R/W |
R/W |
|||
Initial Value |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
|||
The Timer/Counter Register gives direct access, both for read and write operations, to the Timer/Counter unit 8-bit counter. Writing to the TCNT2 Register blocks (removes) the Compare Match on the following timer clock. Modifying the counter (TCNT2) while the counter is running, introduces a risk of missing a Compare Match between TCNT2 and the OCR2 Register.
Bit |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
OCR2[7:0] |
OCR2 |
||||||||
Read/Write |
R/W |
R/W |
R/W |
R/W |
R/W |
R/W |
R/W |
R/W |
|
Initial Value |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
|
The Output Compare Register contains an 8-bit value that is continuously compared with the counter value (TCNT2). A match can be used to generate an Output Compare interrupt, or to generate a waveform output on the OC2 pin.
Asynchronous Operation
of the Timer/Counter
Asynchronous Status
Register – ASSR
Bit |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
– |
– |
– |
– |
AS2 |
TCN2UB |
OCR2UB |
TCR2UB |
ASSR |
|
Read/Write |
R |
R |
R |
R |
R/W |
R |
R |
R |
|
Initial Value |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
• Bit 3 – AS2: Asynchronous Timer/Counter2
When AS2 is written to zero, Timer/Counter 2 is clocked from the I/O clock, clkI/O. When AS2 is written to one, Timer/Counter 2 is clocked from a crystal Oscillator connected to the Timer Oscillator 1 (TOSC1) pin. When the value of AS2 is changed, the contents of TCNT2, OCR2, and TCCR2 might be corrupted.
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Asynchronous Operation of
Timer/Counter2
• Bit 2 – TCN2UB: Timer/Counter2 Update Busy
When Timer/Counter2 operates asynchronously and TCNT2 is written, this bit becomes set. When TCNT2 has been updated from the temporary storage register, this bit is cleared by hardware. A logical zero in this bit indicates that TCNT2 is ready to be updated with a new value.
• Bit 1 – OCR2UB: Output Compare Register2 Update Busy
When Timer/Counter2 operates asynchronously and OCR2 is written, this bit becomes set. When OCR2 has been updated from the temporary storage register, this bit is cleared by hardware. A logical zero in this bit indicates that OCR2 is ready to be updated with a new value.
• Bit 0 – TCR2UB: Timer/Counter Control Register2 Update Busy
When Timer/Counter2 operates asynchronously and TCCR2 is written, this bit becomes set. When TCCR2 has been updated from the temporary storage register, this bit is cleared by hardware. A logical zero in this bit indicates that TCCR2 is ready to be updated with a new value.
If a write is performed to any of the three Timer/Counter2 Registers while its update busy flag is set, the updated value might get corrupted and cause an unintentional interrupt to occur.
The mechanisms for reading TCNT2, OCR2, and TCCR2 are different. When reading TCNT2, the actual timer value is read. When reading OCR2 or TCCR2, the value in the temporary storage register is read.
When Timer/Counter2 operates asynchronously, some considerations must be taken.
•Warning: When switching between asynchronous and synchronous clocking of Timer/Counter2, the Timer Registers TCNT2, OCR2, and TCCR2 might be corrupted. A safe procedure for switching clock source is:
1.Disable the Timer/Counter2 interrupts by clearing OCIE2 and TOIE2.
2.Select clock source by setting AS2 as appropriate.
3.Write new values to TCNT2, OCR2, and TCCR2.
4.To switch to asynchronous operation: Wait for TCN2UB, OCR2UB, and TCR2UB.
5.Clear the Timer/Counter2 Interrupt Flags.
6.Enable interrupts, if needed.
•The Oscillator is optimized for use with a 32.768 kHz watch crystal. Applying an external clock to the TOSC1 pin may result in incorrect Timer/Counter2 operation. The CPU main clock frequency must be more than four times the Oscillator frequency.
•When writing to one of the registers TCNT2, OCR2, or TCCR2, the value is transferred to a temporary register, and latched after two positive edges on TOSC1. The user should not write a new value before the contents of the temporary register have been transferred to its destination. Each of the three mentioned registers have their individual temporary register, which means that e.g. writing to TCNT2 does not disturb an OCR2 write in progress. To detect that a transfer to the destination register has taken place, the Asynchronous Status Register – ASSR has been implemented.
•When entering Power-save mode after having written to TCNT2, OCR2, or TCCR2, the user must wait until the written register has been updated if Timer/Counter2 is used to wake up the device. Otherwise, the MCU will enter sleep mode before the
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ATmega8(L)
changes are effective. This is particularly important if the Output Compare2 interrupt is used to wake up the device, since the Output Compare function is disabled during writing to OCR2 or TCNT2. If the write cycle is not finished, and the MCU enters sleep mode before the OCR2UB bit returns to zero, the device will never receive a Compare Match interrupt, and the MCU will not wake up.
•If Timer/Counter2 is used to wake the device up from Power-save mode, precautions must be taken if the user wants to re-enter one of these modes: The interrupt logic needs one TOSC1 cycle to be reset. If the time between wake-up and re-entering sleep mode is less than one TOSC1 cycle, the interrupt will not occur, and the device will fail to wake up. If the user is in doubt whether the time before reentering Power-save or Extended Standby mode is sufficient, the following algorithm can be used to ensure that one TOSC1 cycle has elapsed:
1.Write a value to TCCR2, TCNT2, or OCR2.
2.Wait until the corresponding Update Busy Flag in ASSR returns to zero.
3.Enter Power-save or Extended Standby mode.
•When the asynchronous operation is selected, the 32.768 kHZ Oscillator for Timer/Counter2 is always running, except in Power-down and Standby modes. After a Power-up Reset or Wake-up from Power-down or Standby mode, the user should be aware of the fact that this Oscillator might take as long as one second to stabilize. The user is advised to wait for at least one second before using Timer/Counter2 after Power-up or Wake-up from Power-down or Standby mode. The contents of all Timer/Counter2 Registers must be considered lost after a wake-up from Powerdown or Standby mode due to unstable clock signal upon start-up, no matter whether the Oscillator is in use or a clock signal is applied to the TOSC1 pin.
•Description of wake up from Power-save or Extended Standby mode when the timer is clocked asynchronously: When the interrupt condition is met, the wake up process is started on the following cycle of the timer clock, that is, the timer is always advanced by at least one before the processor can read the counter value. After wake-up, the MCU is halted for four cycles, it executes the interrupt routine, and resumes execution from the instruction following SLEEP.
•Reading of the TCNT2 Register shortly after wake-up from Power-save may give an incorrect result. Since TCNT2 is clocked on the asynchronous TOSC clock, reading TCNT2 must be done through a register synchronized to the internal I/O clock domain. Synchronization takes place for every rising TOSC1 edge. When waking up
from Power-save mode, and the I/O clock (clkI/O) again becomes active, TCNT2 will read as the previous value (before entering sleep) until the next rising TOSC1 edge. The phase of the TOSC clock after waking up from Power-save mode is essentially unpredictable, as it depends on the wake-up time. The recommended procedure for reading TCNT2 is thus as follows:
1.Write any value to either of the registers OCR2 or TCCR2.
2.Wait for the corresponding Update Busy Flag to be cleared.
3.Read TCNT2.
•During asynchronous operation, the synchronization of the Interrupt Flags for the asynchronous timer takes three processor cycles plus one timer cycle. The timer is therefore advanced by at least one before the processor can read the timer value causing the setting of the Interrupt Flag. The Output Compare Pin is changed on the timer clock and is not synchronized to the processor clock.
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Timer/Counter Interrupt Mask
Register – TIMSK
Bit |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|||||
OCIE2 |
TOIE2 |
TICIE1 |
OCIE1A |
OCIE1B |
TOIE1 |
– |
TOIE0 |
TIMSK |
|||||
Read/Write |
R/W |
R/W |
R/W |
R/W |
R/W |
R/W |
R |
R/W |
|||||
Initial Value |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
|||||
• Bit 7 – OCIE2: Timer/Counter2 Output Compare Match Interrupt Enable
When the OCIE2 bit is written to one and the I-bit in the Status Register is set (one), the Timer/Counter2 Compare Match interrupt is enabled. The corresponding interrupt is executed if a Compare Match in Timer/Counter2 occurs (i.e., when the OCF2 bit is set in the Timer/Counter Interrupt Flag Register – TIFR).
• Bit 6 – TOIE2: Timer/Counter2 Overflow Interrupt Enable
When the TOIE2 bit is written to one and the I-bit in the Status Register is set (one), the Timer/Counter2 Overflow interrupt is enabled. The corresponding interrupt is executed if an overflow in Timer/Counter2 occurs (i.e., when the TOV2 bit is set in the Timer/Counter Interrupt Flag Register – TIFR).
Timer/Counter Interrupt Flag
Register – TIFR
Bit |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
OCF2 |
TOV2 |
ICF1 |
OCF1A |
OCF1B |
TOV1 |
– |
TOV0 |
TIFR |
|
Read/Write |
R/W |
R/W |
R/W |
R/W |
R/W |
R/W |
R |
R/W |
|
Initial Value |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
• Bit 7 – OCF2: Output Compare Flag 2
The OCF2 bit is set (one) when a Compare Match occurs between the Timer/Counter2 and the data in OCR2 – Output Compare Register2. OCF2 is cleared by hardware when executing the corresponding interrupt Handling Vector. Alternatively, OCF2 is cleared by writing a logic one to the flag. When the I-bit in SREG, OCIE2 (Timer/Counter2 Compare Match Interrupt Enable), and OCF2 are set (one), the Timer/Counter2 Compare Match Interrupt is executed.
• Bit 6 – TOV2: Timer/Counter2 Overflow Flag
The TOV2 bit is set (one) when an overflow occurs in Timer/Counter2. TOV2 is cleared by hardware when executing the corresponding interrupt Handling Vector. Alternatively, TOV2 is cleared by writing a logic one to the flag. When the SREG I-bit, TOIE2 (Timer/Counter2 Overflow Interrupt Enable), and TOV2 are set (one), the Timer/Counter2 Overflow interrupt is executed. In PWM mode, this bit is set when Timer/Counter2 changes counting direction at 0x00.
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ATmega8(L)
Timer/Counter Prescaler Figure 56. Prescaler for Timer/Counter2
clkI/O |
clkT2S |
|||||||||||||
10-BIT T/C PRESCALER |
||||||||||||||
TOSC1 |
Clear |
|||||||||||||
|
/8 |
/32 |
/64 |
/128 |
/256 |
/1024 |
|||||||||
|
T2S |
T2S |
T2S |
||||||||||||
|
T2S |
T2S |
T2S |
||||||||||||
AS2 |
clk |
clk |
clk |
clk |
clk |
clk |
||||||||
PSR2 |
||||||||||||||
0 |
||||||||||||||
CS20
CS21
CS22
TIMER/COUNTER2 CLOCK SOURCE clkT2
Special Function IO Register –
SFIOR
The clock source for Timer/Counter2 is named clkT2S. clkT2S is by default connected to the main system I/O clock clkI/O. By setting the AS2 bit in ASSR, Timer/Counter2 is asynchronously clocked from the TOSC1 pin. This enables use of Timer/Counter2 as a Real Time Counter (RTC). When AS2 is set, pins TOSC1 and TOSC2 are disconnected from Port B. A crystal can then be connected between the TOSC1 and TOSC2 pins to serve as an independent clock source for Timer/Counter2. The Oscillator is optimized for use with a 32.768 kHz crystal. Applying an external clock source to TOSC1 is not recommended.
For Timer/Counter2, the possible prescaled selections are: clkT2S/8, clkT2S/32, clkT2S/64,
clkT2S/128, clkT2S/256, and clkT2S/1024. Additionally, clkT2S as well as 0 (stop) may be selected. Setting the PSR2 bit in SFIOR resets the prescaler. This allows the user to
operate with a predictable prescaler.
Bit |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
– |
– |
– |
– |
ACME |
PUD |
PSR2 |
PSR10 |
SFIOR |
|
Read/Write |
R |
R |
R |
R |
R/W |
R/W |
R/W |
R/W |
|
Initial Value |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
• Bit 1 – PSR2: Prescaler Reset Timer/Counter2
When this bit is written to one, the Timer/Counter2 prescaler will be reset. The bit will be cleared by hardware after the operation is performed. Writing a zero to this bit will have no effect. This bit will always be read as zero if Timer/Counter2 is clocked by the internal CPU clock. If this bit is written when Timer/Counter2 is operating in Asynchronous mode, the bit will remain one until the prescaler has been reset.
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