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Serial Peripheral

Interface – SPI

The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the ATmega8 and peripheral devices or between several AVR devices. The ATmega8 SPI includes the following features:

•Full-duplex, Three-wire Synchronous Data Transfer

•Master or Slave Operation

•LSB First or MSB First Data Transfer

•Seven Programmable Bit Rates

•End of Transmission Interrupt Flag

•Write Collision Flag Protection

•Wake-up from Idle Mode

•Double Speed (CK/2) Master SPI Mode

Figure 57. SPI Block Diagram(1)

DIVIDER

/2/4/8/16/32/64/128

SPI2X

Note: 1. Refer to “Pin Configurations” on page 2, and Table 22 on page 56 for SPI pin placement.

The interconnection between Master and Slave CPUs with SPI is shown in Figure 58. The system consists of two Shift Registers, and a Master clock generator. The SPI Master initiates the communication cycle when pulling low the Slave Select SS pin of the desired Slave. Master and Slave prepare the data to be sent in their respective Shift Registers, and the Master generates the required clock pulses on the SCK line to interchange data. Data is always shifted from Master to Slave on the Master Out – Slave In, MOSI, line, and from Slave to Master on the Master In – Slave Out, MISO, line. After each data packet, the Master will synchronize the Slave by pulling high the Slave Select, SS, line.

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When configured as a Master, the SPI interface has no automatic control of the SS line. This must be handled by user software before communication can start. When this is done, writing a byte to the SPI Data Register starts the SPI clock generator, and the hardware shifts the eight bits into the Slave. After shifting one byte, the SPI clock generator stops, setting the end of Transmission Flag (SPIF). If the SPI interrupt enable bit (SPIE) in the SPCR Register is set, an interrupt is requested. The Master may continue to shift the next byte by writing it into SPDR, or signal the end of packet by pulling high the Slave Select, SS line. The last incoming byte will be kept in the Buffer Register for later use.

When configured as a Slave, the SPI interface will remain sleeping with MISO tri-stated as long as the SS pin is driven high. In this state, software may update the contents of the SPI Data Register, SPDR, but the data will not be shifted out by incoming clock pulses on the SCK pin until the SS pin is driven low. As one byte has been completely shifted, the end of Transmission Flag, SPIF is set. If the SPI interrupt enable bit, SPIE, in the SPCR Register is set, an interrupt is requested. The Slave may continue to place new data to be sent into SPDR before reading the incoming data. The last incoming byte will be kept in the Buffer Register for later use.

Figure 58. SPI Master-Slave Interconnection

MSB	MASTER	LSB	MSB	SLAVE	LSB
		MISO	MISO
8 BIT SHIFT REGISTER			8 BIT SHIFT REGISTER
		MOSI	MOSI
					SHIFT
					ENABLE
	SPI	SCK	SCK
CLOCK GENERATOR		SS	SS
		SS	SS
		VCC

The system is single buffered in the transmit direction and double buffered in the receive direction. This means that bytes to be transmitted cannot be written to the SPI Data Register before the entire shift cycle is completed. When receiving data, however, a received character must be read from the SPI Data Register before the next character has been completely shifted in. Otherwise, the first byte is lost.

In SPI Slave mode, the control logic will sample the incoming signal of the SCK pin. To ensure correct sampling of the clock signal, the frequency of the SPI clock should never exceed fosc/4.

When the SPI is enabled, the data direction of the MOSI, MISO, SCK, and SS pins is overridden according to Table 47. For more details on automatic port overrides, refer to “Alternate Port Functions” on page 54.

Table 47. SPI Pin Overrides(1)

Pin			Direction, Master SPI	Direction, Slave SPI

MOSI			User Defined	Input

MISO			Input	User Defined

SCK			User Defined	Input

			User Defined	Input
	SS		User Defined	Input

Note: 1.		See “Port B Pins Alternate Functions” on page 56 for a detailed description of how to

define the direction of the user defined SPI pins.

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The following code examples show how to initialize the SPI as a Master and how to perform a simple transmission. DDR_SPI in the examples must be replaced by the actual Data Direction Register controlling the SPI pins. DD_MOSI, DD_MISO and DD_SCK must be replaced by the actual data direction bits for these pins. E.g. if MOSI is placed on pin PB5, replace DD_MOSI with DDB5 and DDR_SPI with DDRB.

Assembly Code Example(1)

SPI_MasterInit:

; Set MOSI and SCK output, all others input

ldi r17,(1<<DD_MOSI)|(1<<DD_SCK) out DDR_SPI,r17

; Enable SPI, Master, set clock rate fck/16 ldi r17,(1<<SPE)|(1<<MSTR)|(1<<SPR0)

out SPCR,r17 ret

SPI_MasterTransmit:

; Start transmission of data (r16) out SPDR,r16

Wait_Transmit:

; Wait for transmission complete sbis SPSR,SPIF

rjmp Wait_Transmit

ret

C Code Example(1)

void SPI_MasterInit(void)

{

/* Set MOSI and SCK output, all others input */ DDR_SPI = (1<<DD_MOSI)|(1<<DD_SCK);

/* Enable SPI, Master, set clock rate fck/16 */ SPCR = (1<<SPE)|(1<<MSTR)|(1<<SPR0);

}

void SPI_MasterTransmit(char cData)

{

/* Start transmission */ SPDR = cData;

/* Wait for transmission complete */ while(!(SPSR & (1<<SPIF)))

;

}

Note: 1. The example code assumes that the part specific header file is included.

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The following code examples show how to initialize the SPI as a Slave and how to perform a simple reception.

Assembly Code Example(1)

SPI_SlaveInit:

; Set MISO output, all others input

ldi	r17,(1<<DD_MISO)
out	DDR_SPI,r17
; Enable SPI
ldi	r17,(1<<SPE)
out	SPCR,r17
ret

SPI_SlaveReceive:

; Wait for reception complete sbis SPSR,SPIF

rjmp SPI_SlaveReceive

; Read received data and return in r16,SPDR

ret

C Code Example(1)

void SPI_SlaveInit(void)

{

/* Set MISO output, all others input */ DDR_SPI = (1<<DD_MISO);

/* Enable SPI */ SPCR = (1<<SPE);

}

char SPI_SlaveReceive(void)

{

/* Wait for reception complete */ while(!(SPSR & (1<<SPIF)))

;

/* Return data register */ return SPDR;

}

Note: 1. The example code assumes that the part specific header file is included.

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SS Pin Functionality

Slave Mode

When the SPI is configured as a Slave, the Slave Select (SS) pin is always input. When

is held low, the SPI is activated, and MISO becomes an output if configured so by

the user. All other pins are inputs. When

is driven high, all pins are inputs, and the

SPI is passive, which means that it will not receive incoming data. Note that the SPI

logic will be reset once the

pin is driven high.

The

pin is useful for packet/byte synchronization to keep the Slave bit counter syn-

chronous with the master clock generator. When the

pin is driven high, the SPI Slave

will immediately reset the send and receive logic, and drop any partially received data in

the Shift Register.

Master Mode

When the SPI is configured as a Master (MSTR in SPCR is set), the user can determine

the direction of the

pin.

is configured as an output, the pin is a general output pin which does not affect the

SPI system. Typically, the pin will be driving the

pin of the SPI Slave.

is configured as an input, it must be held high to ensure Master SPI operation. If

the

pin is driven low by peripheral circuitry when the SPI is configured as a Master

with the

pin defined as an input, the SPI system interprets this as another Master

selecting the SPI as a Slave and starting to send data to it. To avoid bus contention, the

SPI system takes the following actions:

1. The MSTR bit in SPCR is cleared and the SPI system becomes a Slave. As a

result of the SPI becoming a Slave, the MOSI and SCK pins become inputs.

2. The SPIF Flag in SPSR is set, and if the SPI interrupt is enabled, and the I-bit in

SREG is set, the interrupt routine will be executed.

Thus, when interrupt-driven SPI transmission is used in Master mode, and there exists a

possibility that

is driven low, the interrupt should always check that the MSTR bit is

still set. If the MSTR bit has been cleared by a Slave Select, it must be set by the user to

re-enable SPI Master mode.

SPI Control Register – SPCR

Bit

SPIE

SPE

DORD

MSTR

CPOL

CPHA

SPR1

SPR0

SPCR

Read/Write

R/W

Initial Value

• Bit 7 – SPIE: SPI Interrupt Enable

This bit causes the SPI interrupt to be executed if SPIF bit in the SPSR Register is set and the if the global interrupt enable bit in SREG is set.

• Bit 6 – SPE: SPI Enable

When the SPE bit is written to one, the SPI is enabled. This bit must be set to enable any SPI operations.

• Bit 5 – DORD: Data Order

When the DORD bit is written to one, the LSB of the data word is transmitted first.

When the DORD bit is written to zero, the MSB of the data word is transmitted first.

• Bit 4 – MSTR: Master/Slave Select

This bit selects Master SPI mode when written to one, and Slave SPI mode when written logic zero. If SS is configured as an input and is driven low while MSTR is set, MSTR will

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be cleared, and SPIF in SPSR will become set. The user will then have to set MSTR to re-enable SPI Master mode.

• Bit 3 – CPOL: Clock Polarity

When this bit is written to one, SCK is high when idle. When CPOL is written to zero, SCK is low when idle. Refer to Figure 59 and Figure 60 for an example. The CPOL functionality is summarized below:

Table 48. CPOL Functionality

CPOL	Leading Edge	Trailing Edge

0	Rising	Falling

1	Falling	Rising

• Bit 2 – CPHA: Clock Phase

The settings of the clock phase bit (CPHA) determine if data is sampled on the leading (first) or trailing (last) edge of SCK. Refer to Figure 59 and Figure 60 for an example. The CPHA functionality is summarized below:

Table 49. CPHA Functionality