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SPI Status Register – SPSR
Bit |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
SPIF |
WCOL |
– |
– |
– |
– |
– |
SPI2X |
SPSR |
|
Read/Write |
R |
R |
R |
R |
R |
R |
R |
R/W |
|
Initial Value |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
• Bit 7 – SPIF: SPI Interrupt Flag
When a serial transfer is complete, the SPIF Flag is set. An interrupt is generated if SPIE in SPCR is set and global interrupts are enabled. If SS is an input and is driven low when the SPI is in Master mode, this will also set the SPIF Flag. SPIF is cleared by hardware when executing the corresponding interrupt Handling Vector. Alternatively, the SPIF bit is cleared by first reading the SPI Status Register with SPIF set, then accessing the SPI Data Register (SPDR).
• Bit 6 – WCOL: Write COLlision Flag
The WCOL bit is set if the SPI Data Register (SPDR) is written during a data transfer. The WCOL bit (and the SPIF bit) are cleared by first reading the SPI Status Register with WCOL set, and then accessing the SPI Data Register.
• Bit 5..1 – Res: Reserved Bits
These bits are reserved bits in the ATmega8 and will always read as zero.
• Bit 0 – SPI2X: Double SPI Speed Bit
When this bit is written logic one the SPI speed (SCK Frequency) will be doubled when the SPI is in Master mode (see Table 50). This means that the minimum SCK period will be 2 CPU clock periods. When the SPI is configured as Slave, the SPI is only guaranteed to work at fosc/4 or lower.
The SPI interface on the ATmega8 is also used for Program memory and EEPROM downloading or uploading. See page 234 for Serial Programming and verification.
SPI Data Register – SPDR
Bit |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
0 |
|
MSB |
LSB |
SPDR |
|||||||
Read/Write |
R/W |
R/W |
R/W |
R/W |
R/W |
R/W |
R/W |
R/W |
|
Initial Value |
X |
X |
X |
X |
X |
X |
X |
X |
Undefined |
The SPI Data Register is a Read/Write Register used for data transfer between the Register File and the SPI Shift Register. Writing to the register initiates data transmission. Reading the register causes the Shift Register Receive buffer to be read.
128 ATmega8(L)
2486O–AVR–10/04
ATmega8(L)
Data Modes
There are four combinations of SCK phase and polarity with respect to serial data, which are determined by control bits CPHA and CPOL. The SPI data transfer formats are shown in Figure 59 and Figure 60. Data bits are shifted out and latched in on opposite edges of the SCK signal, ensuring sufficient time for data signals to stabilize. This is clearly seen by summarizing Table 48 and Table 49, as done below:
Table 51. CPOL and CPHA Functionality
Leading Edge |
Trailing Edge |
SPI Mode |
|
CPOL = 0, CPHA = 0 |
Sample (Rising) |
Setup (Falling) |
0 |
CPOL = 0, CPHA = 1 |
Setup (Rising) |
Sample (Falling) |
1 |
CPOL = 1, CPHA = 0 |
Sample (Falling) |
Setup (Rising) |
2 |
CPOL = 1, CPHA = 1 |
Setup (Falling) |
Sample (Rising) |
3 |
Figure 59. SPI Transfer Format with CPHA = 0
SCK (CPOL = 0) mode 0
SCK (CPOL = 1) mode 2
SAMPLE I
MOSI/MISO
CHANGE 0
MOSI PIN
CHANGE 0
MISO PIN
SS
MSB first (DORD = 0) |
MSB |
Bit 6 |
Bit 5 |
Bit 4 |
Bit 3 |
Bit 2 |
Bit 1 |
LSB |
LSB first (DORD = 1) |
LSB |
Bit 1 |
Bit 2 |
Bit 3 |
Bit 4 |
Bit 5 |
Bit 6 |
MSB |
Figure 60. SPI Transfer Format with CPHA = 1
SCK (CPOL = 0) mode 1
SCK (CPOL = 1) mode 3
SAMPLE I
MOSI/MISO
CHANGE 0
MOSI PIN
CHANGE 0
MISO PIN
SS
MSB first (DORD = 0) |
MSB |
Bit 6 |
Bit 5 |
Bit 4 |
Bit 3 |
Bit 2 |
Bit 1 |
LSB |
LSB first (DORD = 1) |
LSB |
Bit 1 |
Bit 2 |
Bit 3 |
Bit 4 |
Bit 5 |
Bit 6 |
MSB |
129
2486O–AVR–10/04
USART
The Universal Synchronous and Asynchronous serial Receiver and Transmitter (USART) is a highly-flexible serial communication device. The main features are:
•Full Duplex Operation (Independent Serial Receive and Transmit Registers)
•Asynchronous or Synchronous Operation
•Master or Slave Clocked Synchronous Operation
•High Resolution Baud Rate Generator
•Supports Serial Frames with 5, 6, 7, 8, or 9 Databits and 1 or 2 Stop Bits
•Odd or Even Parity Generation and Parity Check Supported by Hardware
•Data OverRun Detection
•Framing Error Detection
•Noise Filtering Includes False Start Bit Detection and Digital Low Pass Filter
•Three Separate Interrupts on TX Complete, TX Data Register Empty and RX Complete
•Multi-processor Communication Mode
•Double Speed Asynchronous Communication Mode
Overview |
A simplified block diagram of the USART Transmitter is shown in Figure 61. CPU acces- |
sible I/O Registers and I/O pins are shown in bold. |
|
Figure 61. USART Block Diagram(1) |
DATABUS
Clock Generator
UBRR[H:L]
OSC
BAUD RATE GENERATOR
SYNC LOGIC |
PIN |
XCK |
|||||||||||
CONTROL |
|||||||||||||
Transmitter
UDR (Transmit)
TX
CONTROL
PARITY
GENERATOR
TRANSMIT SHIFT REGISTER |
PIN |
TxD |
|||||||||
CONTROL |
|||||||||||
CLOCK |
RECOVERY |
RECEIVE SHIFT REGISTER |
DATA |
|
RECOVERY |
||
UDR (Receive) |
PARITY |
|
CHECKER |
||
Receiver
RX |
CONTROL |
PIN
RxD
CONTROL
UCSRA |
UCSRB |
UCSRC |
|||||||
Note: 1. Refer to “Pin Configurations” on page 2, Table 30 on page 62, and Table 29 on page 62 for USART pin placement.
130 ATmega8(L)
2486O–AVR–10/04