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Table 62. Examples of UBRR Settings for Commonly Used Oscillator Frequencies (Continued)
Baud |
fosc = 8.0000 MHz |
fosc = 11.0592 MHz |
fosc = 14.7456 MHz |
|||||||||||
U2X = 0 |
U2X = 1 |
U2X = 0 |
U2X = 1 |
U2X = 0 |
U2X = 1 |
|||||||||
Rate |
||||||||||||||
(bps) |
UBRR |
Error |
UBRR |
Error |
UBRR |
Error |
UBRR |
Error |
UBRR |
Error |
UBRR |
Error |
||
2400 |
207 |
0.2% |
416 |
-0.1% |
287 |
0.0% |
575 |
0.0% |
383 |
0.0% |
767 |
0.0% |
||
4800 |
103 |
0.2% |
207 |
0.2% |
143 |
0.0% |
287 |
0.0% |
191 |
0.0% |
383 |
0.0% |
||
9600 |
51 |
0.2% |
103 |
0.2% |
71 |
0.0% |
143 |
0.0% |
95 |
0.0% |
191 |
0.0% |
||
14.4k |
34 |
-0.8% |
68 |
0.6% |
47 |
0.0% |
95 |
0.0% |
63 |
0.0% |
127 |
0.0% |
||
19.2k |
25 |
0.2% |
51 |
0.2% |
35 |
0.0% |
71 |
0.0% |
47 |
0.0% |
95 |
0.0% |
||
28.8k |
16 |
2.1% |
34 |
-0.8% |
23 |
0.0% |
47 |
0.0% |
31 |
0.0% |
63 |
0.0% |
||
38.4k |
12 |
0.2% |
25 |
0.2% |
17 |
0.0% |
35 |
0.0% |
23 |
0.0% |
47 |
0.0% |
||
57.6k |
8 |
-3.5% |
16 |
2.1% |
11 |
0.0% |
23 |
0.0% |
15 |
0.0% |
31 |
0.0% |
||
76.8k |
6 |
-7.0% |
12 |
0.2% |
8 |
0.0% |
17 |
0.0% |
11 |
0.0% |
23 |
0.0% |
||
115.2k |
3 |
8.5% |
8 |
-3.5% |
5 |
0.0% |
11 |
0.0% |
7 |
0.0% |
15 |
0.0% |
||
230.4k |
1 |
8.5% |
3 |
8.5% |
2 |
0.0% |
5 |
0.0% |
3 |
0.0% |
7 |
0.0% |
||
250k |
1 |
0.0% |
3 |
0.0% |
2 |
-7.8% |
5 |
-7.8% |
3 |
-7.8% |
6 |
5.3% |
||
0.5M |
0 |
0.0% |
1 |
0.0% |
– |
– |
2 |
-7.8% |
1 |
-7.8% |
3 |
-7.8% |
||
1M |
– |
– |
0 |
0.0% |
– |
– |
– |
– |
0 |
-7.8% |
1 |
-7.8% |
||
Max (1) |
0.5 Mbps |
1 Mbps |
691.2 kbps |
1.3824 Mbps |
921.6 kbps |
1.8432 Mbps |
||||||||
1.UBRR = 0, Error = 0.0%
158 ATmega8(L)
2486O–AVR–10/04
ATmega8(L)
Table 63. Examples of UBRR Settings for Commonly Used Oscillator Frequencies (Continued)
Baud |
fosc = 16.0000 MHz |
fosc = 18.4320 MHz |
fosc = 20.0000 MHz |
||||||||||
U2X = 0 |
U2X = 1 |
U2X = 0 |
U2X = 1 |
U2X = 0 |
U2X = 1 |
||||||||
Rate |
|||||||||||||
(bps) |
UBRR |
Error |
UBRR |
Error |
UBRR |
Error |
UBRR |
Error |
UBRR |
Error |
UBRR |
Error |
|
2400 |
416 |
-0.1% |
832 |
0.0% |
479 |
0.0% |
959 |
0.0% |
520 |
0.0% |
1041 |
0.0% |
|
4800 |
207 |
0.2% |
416 |
-0.1% |
239 |
0.0% |
479 |
0.0% |
259 |
0.2% |
520 |
0.0% |
|
9600 |
103 |
0.2% |
207 |
0.2% |
119 |
0.0% |
239 |
0.0% |
129 |
0.2% |
259 |
0.2% |
|
14.4k |
68 |
0.6% |
138 |
-0.1% |
79 |
0.0% |
159 |
0.0% |
86 |
-0.2% |
173 |
-0.2% |
|
19.2k |
51 |
0.2% |
103 |
0.2% |
59 |
0.0% |
119 |
0.0% |
64 |
0.2% |
129 |
0.2% |
|
28.8k |
34 |
-0.8% |
68 |
0.6% |
39 |
0.0% |
79 |
0.0% |
42 |
0.9% |
86 |
-0.2% |
|
38.4k |
25 |
0.2% |
51 |
0.2% |
29 |
0.0% |
59 |
0.0% |
32 |
-1.4% |
64 |
0.2% |
|
57.6k |
16 |
2.1% |
34 |
-0.8% |
19 |
0.0% |
39 |
0.0% |
21 |
-1.4% |
42 |
0.9% |
|
76.8k |
12 |
0.2% |
25 |
0.2% |
14 |
0.0% |
29 |
0.0% |
15 |
1.7% |
32 |
-1.4% |
|
115.2k |
8 |
-3.5% |
16 |
2.1% |
9 |
0.0% |
19 |
0.0% |
10 |
-1.4% |
21 |
-1.4% |
|
230.4k |
3 |
8.5% |
8 |
-3.5% |
4 |
0.0% |
9 |
0.0% |
4 |
8.5% |
10 |
-1.4% |
|
250k |
3 |
0.0% |
7 |
0.0% |
4 |
-7.8% |
8 |
2.4% |
4 |
0.0% |
9 |
0.0% |
|
0.5M |
1 |
0.0% |
3 |
0.0% |
– |
– |
4 |
-7.8% |
– |
– |
4 |
0.0% |
|
1M |
0 |
0.0% |
1 |
0.0% |
– |
– |
– |
– |
– |
– |
– |
– |
|
Max (1) |
1 Mbps |
2 Mbps |
1.152 Mbps |
2.304 Mbps |
1.25 Mbps |
2.5 Mbps |
|||||||
1.UBRR = 0, Error = 0.0%
159
2486O–AVR–10/04
Two-wire Serial
Interface
Features
•Simple Yet Powerful and Flexible Communication Interface, only two Bus Lines Needed
•Both Master and Slave Operation Supported
•Device can Operate as Transmitter or Receiver
•7-bit Address Space Allows up to 128 Different Slave Addresses
•Multi-master Arbitration Support
•Up to 400 kHz Data Transfer Speed
•Slew-rate Limited Output Drivers
•Noise Suppression Circuitry Rejects Spikes on Bus Lines
•Fully Programmable Slave Address with General Call Support
•Address Recognition Causes Wake-up When AVR is in Sleep Mode
Two-wire Serial Interface
Bus Definition
The Two-wire Serial Interface (TWI) is ideally suited for typical microcontroller applications. The TWI protocol allows the systems designer to interconnect up to 128 different devices using only two bi-directional bus lines, one for clock (SCL) and one for data (SDA). The only external hardware needed to implement the bus is a single pull-up resistor for each of the TWI bus lines. All devices connected to the bus have individual addresses, and mechanisms for resolving bus contention are inherent in the TWI protocol.
Figure 68. TWI Bus Interconnection
VCC
Device 1 |
Device 3 |
|||||||||
Device 2 |
........ |
Device n |
R1 |
R2 |
||||||
SDA |
||||
TWI Terminology |
SCL |
|||
The following definitions are frequently encountered in this section. |
||||
Table 64. TWI Terminology |
||||
Term |
Description |
|||
Master |
The device that initiates and terminates a transmission. The Master also |
|||
generates the SCL clock. |
||||
Slave |
The device addressed by a Master. |
|||
Transmitter |
The device placing data on the bus. |
|||
Receiver |
The device reading data from the bus. |
|||
160 ATmega8(L)
2486O–AVR–10/04
ATmega8(L) |
|||||
Electrical Interconnection |
|||||
As depicted in Figure 68, both bus lines are connected to the positive supply voltage |
|||||
through pull-up resistors. The bus drivers of all TWI-compliant devices are open-drain or |
|||||
open-collector. This implements a wired-AND function which is essential to the opera- |
|||||
tion of the interface. A low level on a TWI bus line is generated when one or more TWI |
|||||
devices output a zero. A high level is output when all TWI devices tri-state their outputs, |
|||||
allowing the pull-up resistors to pull the line high. Note that all AVR devices connected to |
|||||
the TWI bus must be powered in order to allow any bus operation. |
|||||
The number of devices that can be connected to the bus is only limited by the bus |
|||||
capacitance limit of 400 pF and the 7-bit slave address space. A detailed specification of |
|||||
the electrical characteristics of the TWI is given in “Two-wire Serial Interface Character- |
|||||
istics” on page 242. Two different sets of specifications are presented there, one |
|||||
relevant for bus speeds below 100 kHz, and one valid for bus speeds up to 400 kHz. |
|||||
Data Transfer and Frame |
|||||
Format |
|||||
Transferring Bits |
Each data bit transferred on the TWI bus is accompanied by a pulse on the clock line. |
||||
The level of the data line must be stable when the clock line is high. The only exception |
|||||
to this rule is for generating start and stop conditions. |
|||||
Figure 69. Data Validity |
|||||
SDA |
|||||
SCL
Data Stable |
Data Stable |
Data Change
START and STOP Conditions The Master initiates and terminates a data transmission. The transmission is initiated when the Master issues a START condition on the bus, and it is terminated when the Master issues a STOP condition. Between a START and a STOP condition, the bus is considered busy, and no other master should try to seize control of the bus. A special case occurs when a new START condition is issued between a START and STOP condition. This is referred to as a REPEATED START condition, and is used when the Master wishes to initiate a new transfer without relinquishing control of the bus. After a REPEATED START, the bus is considered busy until the next STOP. This is identical to the START behavior, and therefore START is used to describe both START and REPEATED START for the remainder of this datasheet, unless otherwise noted. As depicted below, START and STOP conditions are signalled by changing the level of the SDA line when the SCL line is high.
161
2486O–AVR–10/04