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				ATmega8(L)

Bit Rate Generator Unit
	This unit controls the period of SCL when operating in a Master mode. The SCL period

	is controlled by settings in the TWI Bit Rate Register (TWBR) and the Prescaler bits in
	the TWI Status Register (TWSR). Slave operation does not depend on Bit Rate or Pres-
	caler settings, but the CPU clock frequency in the Slave must be at least 16 times higher
	than the SCL frequency. Note that slaves may prolong the SCL low period, thereby
	reducing the average TWI bus clock period. The SCL frequency is generated according
	to the following equation:
		SCL frequency = CPU Clock frequency----------------------------------------------------------
			16 + 2(TWBR) 4TWPS
	• TWBR = Value of the TWI Bit Rate Register.
	• TWPS = Value of the prescaler bits in the TWI Status Register.
	Note: TWBR should be 10 or higher if the TWI operates in Master mode. If TWBR is lower than
	10, the Master may produce an incorrect output on SDA and SCL for the reminder of the
	byte. The problem occurs when operating the TWI in Master mode, sending Start + SLA
	+ R/W to a Slave (a Slave does not need to be connected to the bus for the condition to
	happen).
Bus Interface Unit	This unit contains the Data and Address Shift Register (TWDR), a START/STOP Con-
	troller and Arbitration detection hardware. The TWDR contains the address or data
	bytes to be transmitted, or the address or data bytes received. In addition to the 8-bit
	TWDR, the Bus Interface Unit also contains a register containing the (N)ACK bit to be
	transmitted or received. This (N)ACK Register is not directly accessible by the applica-
	tion software. However, when receiving, it can be set or cleared by manipulating the
	TWI Control Register (TWCR). When in Transmitter mode, the value of the received
	(N)ACK bit can be determined by the value in the TWSR.
	The START/STOP Controller is responsible for generation and detection of START,
	REPEATED START, and STOP conditions. The START/STOP controller is able to
	detect START and STOP conditions even when the AVR MCU is in one of the sleep
	modes, enabling the MCU to wake up if addressed by a Master.
	If the TWI has initiated a transmission as Master, the Arbitration Detection hardware
	continuously monitors the transmission trying to determine if arbitration is in process. If
	the TWI has lost an arbitration, the Control Unit is informed. Correct action can then be
	taken and appropriate status codes generated.
Address Match Unit	The Address Match unit checks if received address bytes match the seven-bit address
	in the TWI Address Register (TWAR). If the TWI General Call Recognition Enable
	(TWGCE) bit in the TWAR is written to one, all incoming address bits will also be com-
	pared against the General Call address. Upon an address match, the Control Unit is
	informed, allowing correct action to be taken. The TWI may or may not acknowledge its
	address, depending on settings in the TWCR. The Address Match unit is able to com-
	pare addresses even when the AVR MCU is in sleep mode, enabling the MCU to wake
	up if addressed by a Master. If another interrupt (e.g., INT0) occurs during TWI Power-
	down address match and wakes up the CPU, the TWI aborts operation and return to it’s
	idle state. If this cause any problems, ensure that TWI Address Match is the only
	enabled interrupt when entering Power-down.
Control Unit	The Control unit monitors the TWI bus and generates responses corresponding to set-
	tings in the TWI Control Register (TWCR). When an event requiring the attention of the
	application occurs on the TWI bus, the TWI Interrupt Flag (TWINT) is asserted. In the
	next clock cycle, the TWI Status Register (TWSR) is updated with a status code identify-
	ing the event. The TWSR only contains relevant status information when the TWI

			167
2486O–AVR–10/04			167
2486O–AVR–10/04

Interrupt Flag is asserted. At all other times, the TWSR contains a special status code indicating that no relevant status information is available. As long as the TWINT Flag is set, the SCL line is held low. This allows the application software to complete its tasks before allowing the TWI transmission to continue.

The TWINT Flag is set in the following situations:

•After the TWI has transmitted a START/REPEATED START condition.

•After the TWI has transmitted SLA+R/W.

•After the TWI has transmitted an address byte.

•After the TWI has lost arbitration.

•After the TWI has been addressed by own slave address or general call.

•After the TWI has received a data byte.

•After a STOP or REPEATED START has been received while still addressed as a Slave.

•When a bus error has occurred due to an illegal START or STOP condition.

TWI Register Description

TWI Bit Rate Register – TWBR

Bit	7	6	5	4	3	2	1	0
	TWBR7	TWBR6	TWBR5	TWBR4	TWBR3	TWBR2	TWBR1	TWBR0	TWBR
Read/Write	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Initial Value	0	0	0	0	0	0	0	0

• Bits 7..0 – TWI Bit Rate Register

TWBR selects the division factor for the bit rate generator. The bit rate generator is a frequency divider which generates the SCL clock frequency in the Master modes. See “Bit Rate Generator Unit” on page 167 for calculating bit rates.

TWI Control Register – TWCR

Bit	7	6	5	4	3	2	1	0
	TWINT	TWEA	TWSTA	TWSTO	TWWC	TWEN	–	TWIE	TWCR
Read/Write	R/W	R/W	R/W	R/W	R	R/W	R	R/W
Initial Value	0	0	0	0	0	0	0	0

The TWCR is used to control the operation of the TWI. It is used to enable the TWI, to initiate a Master access by applying a START condition to the bus, to generate a Receiver acknowledge, to generate a stop condition, and to control halting of the bus while the data to be written to the bus are written to the TWDR. It also indicates a write collision if data is attempted written to TWDR while the register is inaccessible.

• Bit 7 – TWINT: TWI Interrupt Flag

This bit is set by hardware when the TWI has finished its current job and expects application software response. If the I-bit in SREG and TWIE in TWCR are set, the MCU will jump to the TWI Interrupt Vector. While the TWINT Flag is set, the SCL low period is stretched. The TWINT Flag must be cleared by software by writing a logic one to it. Note that this flag is not automatically cleared by hardware when executing the interrupt routine. Also note that clearing this flag starts the operation of the TWI, so all accesses to the TWI Address Register (TWAR), TWI Status Register (TWSR), and TWI Data Register (TWDR) must be complete before clearing this flag.

• Bit 6 – TWEA: TWI Enable Acknowledge Bit

168 ATmega8(L)

2486O–AVR–10/04

ATmega8(L)

The TWEA bit controls the generation of the acknowledge pulse. If the TWEA bit is written to one, the ACK pulse is generated on the TWI bus if the following conditions are met:

1.The device’s own slave address has been received.

2.A general call has been received, while the TWGCE bit in the TWAR is set.

3.A data byte has been received in Master Receiver or Slave Receiver mode.

By writing the TWEA bit to zero, the device can be virtually disconnected from the Twowire Serial Bus temporarily. Address recognition can then be resumed by writing the TWEA bit to one again.

• Bit 5 – TWSTA: TWI START Condition Bit

The application writes the TWSTA bit to one when it desires to become a Master on the Two-wire Serial Bus. The TWI hardware checks if the bus is available, and generates a START condition on the bus if it is free. However, if the bus is not free, the TWI waits until a STOP condition is detected, and then generates a new START condition to claim the bus Master status. TWSTA must be cleared by software when the START condition has been transmitted.

• Bit 4 – TWSTO: TWI STOP Condition Bit

Writing the TWSTO bit to one in Master mode will generate a STOP condition on the Two-wire Serial Bus. When the STOP condition is executed on the bus, the TWSTO bit is cleared automatically. In Slave mode, setting the TWSTO bit can be used to recover from an error condition. This will not generate a STOP condition, but the TWI returns to a well-defined unaddressed Slave mode and releases the SCL and SDA lines to a high impedance state.

• Bit 3 – TWWC: TWI Write Collision Flag

The TWWC bit is set when attempting to write to the TWI Data Register – TWDR when

TWINT is low. This flag is cleared by writing the TWDR Register when TWINT is high.

• Bit 2 – TWEN: TWI Enable Bit

The TWEN bit enables TWI operation and activates the TWI interface. When TWEN is written to one, the TWI takes control over the I/O pins connected to the SCL and SDA pins, enabling the slew-rate limiters and spike filters. If this bit is written to zero, the TWI is switched off and all TWI transmissions are terminated, regardless of any ongoing operation.

• Bit 1 – Res: Reserved Bit

This bit is a reserved bit and will always read as zero.

• Bit 0 – TWIE: TWI Interrupt Enable

When this bit is written to one, and the I-bit in SREG is set, the TWI interrupt request will be activated for as long as the TWINT Flag is high.

169

2486O–AVR–10/04

TWI Status Register – TWSR

Bit	7	6	5	4	3	2	1	0
	TWS7	TWS6	TWS5	TWS4	TWS3	–	TWPS1	TWPS0	TWSR
Read/Write	R	R	R	R	R	R	R/W	R/W
Initial Value	1	1	1	1	1	0	0	0

• Bits 7..3 – TWS: TWI Status

These 5 bits reflect the status of the TWI logic and the Two-wire Serial Bus. The different status codes are described later in this section. Note that the value read from TWSR contains both the 5-bit status value and the 2-bit prescaler value. The application designer should mask the prescaler bits to zero when checking the Status bits. This makes status checking independent of prescaler setting. This approach is used in this datasheet, unless otherwise noted.

• Bit 2 – Res: Reserved Bit

This bit is reserved and will always read as zero.

• Bits 1..0 – TWPS: TWI Prescaler Bits

These bits can be read and written, and control the bit rate prescaler.

Table 65. TWI Bit Rate Prescaler

TWPS1	TWPS0	Prescaler Value

0	0	1

0	1	4

1	0	16

1	1	64

To calculate bit rates, see “Bit Rate Generator Unit” on page 167. The value of

TWPS1..0 is used in the equation.

TWI Data Register – TWDR

Bit	7	6	5	4	3	2	1	0
	TWD7	TWD6	TWD5	TWD4	TWD3	TWD2	TWD1	TWD0	TWDR
Read/Write	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Initial Value	1	1	1	1	1	1	1	1

In Transmit mode, TWDR contains the next byte to be transmitted. In Receive mode, the TWDR contains the last byte received. It is writable while the TWI is not in the process of shifting a byte. This occurs when the TWI Interrupt Flag (TWINT) is set by hardware. Note that the Data Register cannot be initialized by the user before the first interrupt occurs. The data in TWDR remains stable as long as TWINT is set. While data is shifted out, data on the bus is simultaneously shifted in. TWDR always contains the last byte present on the bus, except after a wake up from a sleep mode by the TWI interrupt. In this case, the contents of TWDR is undefined. In the case of a lost bus arbitration, no data is lost in the transition from Master to Slave. Handling of the ACK bit is controlled automatically by the TWI logic, the CPU cannot access the ACK bit directly.

• Bits 7..0 – TWD: TWI Data Register

These eight bits constitute the next data byte to be transmitted, or the latest data byte received on the Two-wire Serial Bus.