ВУЗ: Не указан
Категория: Не указан
Дисциплина: Не указана
Добавлен: 02.06.2025
Просмотров: 3622
Скачиваний: 0
Figure 70. START, REPEATED START and STOP conditions
SDA |
||||
SCL |
||||
START |
STOP START |
REPEATED START |
STOP |
|
Address Packet Format |
All address packets transmitted on the TWI bus are 9 bits long, consisting of 7 address |
|||
bits, one READ/WRITE control bit and an acknowledge bit. If the READ/WRITE bit is |
||||
set, a read operation is to be performed, otherwise a write operation should be per- |
||||
formed. When a Slave recognizes that it is being addressed, it should acknowledge by |
||||
pulling SDA low in the ninth SCL (ACK) cycle. If the addressed Slave is busy, or for some other reason can not service the Master’s request, the SDA line should be left high in the ACK clock cycle. The Master can then transmit a STOP condition, or a REPEATED START condition to initiate a new transmission. An address packet consisting of a slave address and a READ or a WRITE bit is called SLA+R or SLA+W, respectively.
The MSB of the address byte is transmitted first. Slave addresses can freely be allocated by the designer, but the address 0000 000 is reserved for a general call.
When a general call is issued, all slaves should respond by pulling the SDA line low in the ACK cycle. A general call is used when a Master wishes to transmit the same message to several slaves in the system. When the general call address followed by a Write bit is transmitted on the bus, all slaves set up to acknowledge the general call will pull the SDA line low in the ack cycle. The following data packets will then be received by all the slaves that acknowledged the general call. Note that transmitting the general call address followed by a Read bit is meaningless, as this would cause contention if several slaves started transmitting different data.
All addresses of the format 1111 xxx should be reserved for future purposes.
Figure 71. Address Packet Format
Addr MSB |
Addr LSB R/W |
ACK |
|
SDA
SCL
1 |
2 |
7 |
8 |
9 |
START
162 ATmega8(L)
2486O–AVR–10/04
ATmega8(L) |
|||
Data Packet Format |
|||
All data packets transmitted on the TWI bus are nine bits long, consisting of one data |
|||
byte and an acknowledge bit. During a data transfer, the Master generates the clock and |
|||
the START and STOP conditions, while the Receiver is responsible for acknowledging |
|||
the reception. An Acknowledge (ACK) is signalled by the Receiver pulling the SDA line |
|||
low during the ninth SCL cycle. If the Receiver leaves the SDA line high, a NACK is sig- |
|||
nalled. When the Receiver has received the last byte, or for some reason cannot receive |
|||
any more bytes, it should inform the Transmitter by sending a NACK after the final byte. |
|||
The MSB of the data byte is transmitted first. |
|||
Figure 72. Data Packet Format |
|||
Data MSB Data LSB ACK
Aggregate
SDA
SDA from
Transmitter
SDA from
Receiver
SCL from
Master
1 |
2 |
7 |
8 |
9 |
STOP, REPEATED |
SLA+R/W |
Data Byte |
START or Next |
|||
Data Byte |
Combining Address and Data A transmission basically consists of a START condition, a SLA+R/W, one or more data Packets into a Transmission packets and a STOP condition. An empty message, consisting of a START followed by a STOP condition, is illegal. Note that the Wired-ANDing of the SCL line can be used to implement handshaking between the Master and the Slave. The Slave can extend the SCL low period by pulling the SCL line low. This is useful if the clock speed set up by the Master is too fast for the Slave, or the Slave needs extra time for processing between the data transmissions. The Slave extending the SCL low period will not affect the SCL high period, which is determined by the Master. As a consequence, the Slave can
reduce the TWI data transfer speed by prolonging the SCL duty cycle.
Figure 73 shows a typical data transmission. Note that several data bytes can be transmitted between the SLA+R/W and the STOP condition, depending on the software protocol implemented by the application software.
Figure 73. Typical Data Transmission
Addr MSB |
Addr LSB R/W |
ACK |
Data MSB |
Data LSB ACK |
||
SDA
SCL
1 |
2 |
7 |
8 |
9 |
1 |
2 |
7 |
8 |
9 |
START |
SLA+R/W |
Data Byte |
STOP |
163
2486O–AVR–10/04
Multi-master Bus
Systems, Arbitration and
Synchronization
The TWI protocol allows bus systems with several masters. Special concerns have been taken in order to ensure that transmissions will proceed as normal, even if two or more masters initiate a transmission at the same time. Two problems arise in multi-mas- ter systems:
•An algorithm must be implemented allowing only one of the masters to complete the transmission. All other masters should cease transmission when they discover that they have lost the selection process. This selection process is called arbitration.
When a contending master discovers that it has lost the arbitration process, it should immediately switch to Slave mode to check whether it is being addressed by the winning master. The fact that multiple masters have started transmission at the same time should not be detectable to the slaves, i.e. the data being transferred on the bus must not be corrupted.
•Different masters may use different SCL frequencies. A scheme must be devised to synchronize the serial clocks from all masters, in order to let the transmission proceed in a lockstep fashion. This will facilitate the arbitration process.
The wired-ANDing of the bus lines is used to solve both these problems. The serial clocks from all masters will be wired-ANDed, yielding a combined clock with a high period equal to the one from the Master with the shortest high period. The low period of the combined clock is equal to the low period of the Master with the longest low period. Note that all masters listen to the SCL line, effectively starting to count their SCL high and low time-out periods when the combined SCL line goes high or low, respectively.
Figure 74. SCL Synchronization Between Multiple Masters
TA low |
TA high |
SCL from
Master A
SCL from
Master B
SCL Bus
Line
TBlow |
TBhigh |
|||
Masters Start |
Masters Start |
|||
Counting Low Period |
Counting High Period |
|||
Arbitration is carried out by all masters continuously monitoring the SDA line after outputting data. If the value read from the SDA line does not match the value the Master had output, it has lost the arbitration. Note that a Master can only lose arbitration when it outputs a high SDA value while another Master outputs a low value. The losing Master should immediately go to Slave mode, checking if it is being addressed by the winning Master. The SDA line should be left high, but losing masters are allowed to generate a clock signal until the end of the current data or address packet. Arbitration will continue until only one Master remains, and this may take many bits. If several masters are trying to address the same Slave, arbitration will continue into the data packet.
164 ATmega8(L)
2486O–AVR–10/04
ATmega8(L)
Figure 75. Arbitration Between Two Masters
START
SDA from
Master A
SDA from
Master B
SDA Line
Synchronized
SCL Line
Note that arbitration is not allowed between:
Master A Loses
Arbitration, SDAA SDA
•A REPEATED START condition and a data bit.
•A STOP condition and a data bit.
•A REPEATED START and a STOP condition.
It is the user software’s responsibility to ensure that these illegal arbitration conditions never occur. This implies that in multi-master systems, all data transfers must use the same composition of SLA+R/W and data packets. In other words: All transmissions must contain the same number of data packets, otherwise the result of the arbitration is undefined.
165
2486O–AVR–10/04
Overview of the TWI
Module
SCL and SDA Pins
The TWI module is comprised of several submodules, as shown in Figure 76. All registers drawn in a thick line are accessible through the AVR data bus.
Figure 76. Overview of the TWI Module
SCL |
SDA |
|||
Slew-rate |
Spike |
Slew-rate |
Spike |
|
Control |
Filter |
Control |
Filter |
|
Bus Interface Unit |
Bit Rate Generator |
|||
START / STOP |
Spike Suppression |
Prescaler |
||
Control |
||||
Arbitration detection |
Address/Data Shift |
Ack |
Bit Rate Register |
|
Register (TWDR) |
(TWBR) |
|||
Address Match Unit |
Control Unit |
|||
Address Register |
Status Register |
Control Register |
TWI Unit |
|
(TWAR) |
(TWSR) |
(TWCR) |
||
Address Comparator |
State Machine and |
|||
Status control |
||||
These pins interface the AVR TWI with the rest of the MCU system. The output drivers contain a slew-rate limiter in order to conform to the TWI specification. The input stages contain a spike suppression unit removing spikes shorter than 50 ns. Note that the internal pull-ups in the AVR pads can be enabled by setting the PORT bits corresponding to the SCL and SDA pins, as explained in the I/O Port section. The internal pull-ups can in some systems eliminate the need for external ones.
166 ATmega8(L)
2486O–AVR–10/04