Файл: Digital design with CPLD applications and VHDL (R. Dueck, 2000).pdf

—— Makes one and only one output HIGH for each

—— binary combination of (d1, d0).

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

ENTITY decode2a IS

PORT (

d : IN STD_LOGIC_VECTOR (1 downto 0); y : OUT STD_LOGIC_VECTOR (3 downto 0));

END decode2a;

ARCHITECTURE decoder OF decode2a IS

BEGIN

——Choose a signal assignment for y

——based on binary value of d

——Default case: all outputs deactivated WITH d SELECT

y <= “0001” WHEN “00”, “0010” WHEN “01”, “0100” WHEN “10”, “1000” WHEN “11”, “0000” WHEN others;

END decoder;

In Case 3, we use a selected signal assignment statement to assign a value to all bits of vector y for each combined value of vector d. For example, when d(1) 0 and d(0) 0, the values assigned to y are: y(3) 1, y(2) 0, y(1) 0, y(0) 0. Similar assignments are made for other values of d. The result is a construct that acts much like a truth table of the decoder circuit. The others clause is necessary to define a default case

FIGURE 4.32

MAX PLUS II Template Menu

FIGURE 4.33

VHDL Template Dialog Box

Default Symbol. We can integrate this new symbol into a two-level majority vote circuit, as shown in Figure 4.34. This circuit contains primitives (AND gate, input pins, and output pin), a gdf symbol (maj_vote), and a symbol created from a VHDL file (MAJ_VOT2). Double-clicking on either symbol will bring forward its original design file.

4.7 Creating a Physical Design

K E Y T E R M S

Assignment and Configuration File (acf) A MAX PLUS II file that contains information about the configuration options for a project, including assigned device and pin numbers.

FIGURE 4.35

Pop-up Menu for Pin Assignments

The previous sections have concentrated on the design aspects of a project. Of course, the ultimate goal of this procedure is to create a physical version of the design. Before we can program our majority vote circuit into hardware, we must assign the input and output pin numbers on the target CPLD. At that point we can recompile the design file and program the CPLD.

Assigning Pin Numbers

Before proceeding with this step, make sure that you have assigned a device part number to the design. Save the file and set the project to the current file.

To assign a pin number, click on the pin to highlight it, then right-click to see the popup menu in Figure 4.35. Choose Assign, then Pin/Location/Chip. You could also do this from the Assign menu at the top of the screen.

142 C H A P T E R 4 • Introduction to PLDs and MAX+PLUS II

FIGURE 4.36

Pin/Location/Chip Assignment

Dialog Box

Table 4.2 Pin Assignment for a Majority Vote Circuit

FIGURE 4.37

Pin Assignments in ACF (Before

Copying)

FIGURE 4.38

Pin Assignments in ACF (After Copying)

FIGURE 4.39

Pin Assignments as Seen in gdf File

We can assign pin numbers in the dialog box in Figure 4.36.

Type A1 in the Node Name box, 12 in the Pin box and click Add. Type B1 in the Node Name box, assign this name to pin 16, and click Add. Repeat this procedure until all names are assigned, as in Table 4.2. When all assignments are complete, click OK.

We can also assign pin numbers by editing the Assignment and Configuration File (acf), as shown in Figures 4.37 and 4.38. This technique works especially well if you need to assign pin numbers to a sequence of numerically related inputs and outputs.

Figure 4.37 shows the acf with four pin assignments made. We can add the others easily by using a copy-and-paste procedure. Highlight the line you wish to copy and copy it to the Windows clipboard (use Copy in the File menu or the Copy icon on the toolbar or Ctrl-C). Paste three copies into the acf and modify them so that they represent the remaining required pin assignments, as shown in Figure 4.38.

Figure 4.39 shows the input pin assignments as they appear in the gdf file.