Файл: Digital design with CPLD applications and VHDL (R. Dueck, 2000).pdf

JTAG Chain Multiple JTAG-compliant devices whose TDI and TDO ports form a continuous chain connection. Such a chain allows multi-device programming.

Library A collection of VHDL design units that have been previously compiled.

MAX PLUS II CPLD design and programming software owned by Altera Corporation.

Mode (of a port) The kind of port, such as input or output.

Nonvolatile Able to retain stored information after power is removed.

Package A group of VHDL design elements that can be used by more than one VHDL file.

Port A name assigned to an input or output of a VHDL design entity.

Programmable logic device (PLD) A digital integrated circuit that can be programmed by the user to implement any digital logic function.

Programmer Object File (pof) Binary file used to program a PLD of the Altera MAX series.

Project A set of MAX PLUS II files associated with a particular PLD design.

Schematic capture A technique of entering CPLD design information by using a CAD (computer aided design) tool to draw a logic circuit as a schematic. The schematic can then be interpreted by design software to generate programming information for the CPLD.

Selected signal assignment statement A concurrent signal assignment in VHDL in which a value is assigned to a signal, depending on the alternative values of another signal or variable.

Signal A name given to an internal connection in a VHDL architecture.

Simulation Verifying design function by specifying a set of inputs and observing the resultant outputs. Simulation is generally shown as a series of input and output waveforms.

S0

S1

D0

D1

Y

D2

D3

FIGURE 4.48

Problem 4.4

4-to-1 Multiplexer

Software tools Specialized computer programs used to perform specific functions such as design entry, compiling, fitting, and so on. (Sometimes just called “tools”.)

SRAM Object File (sof) Binary file used to configure a PLD of the Altera FLEX series.

Suite (of software tools) A related collection of tools for performing specific tasks. MAX PLUS II is a suite of tools for de-

signing and programming digital functions in a PLD.

Syntax The “grammar” of a computer language (i.e., the rules of construction of language statements).

Target device The specific PLD for which a digital design is intended.

TCK Test Clock. The JTAG signal that drives the JTAG downloading process from one state to the next.

Table 4.3 Pin Assignments for

Multiplexer Circuit

TDI Test Data In. In a JTAG port, the serial input data to a device.

TDO Test Data Out. The JTAG signal, the serial output data from a device.

FIGURE 4.49

Problem 4.9

4-channel Demultiplexer

TMS Test Mode Select. The JTAG signal that controls the downloading of test or programming data.

Top level (of a hierarchy) The file in a hierarchy that contains components specified in other design files and is not itself a component of a higher-level file.

Table 4.4 Pin Assignments for Demultiplexer Circuit

Table 4.5 Pin Assignments for Equality Comparator

a gdf file.

Variable A block of working memory used for internal calculation or storage in a VHDL architecture.

Vector A group of digital signals or variables, usually related numerically, that can be treated as a single multi-bit variable.

VHDL (VHSIC Hardware Description Language) An in-

Type A set of characteristics associated with a VHDL port name, signal, or variable that determines the allowable values of the port, signal, or variable.

User library A folder containing symbols that can be used in

A

SUM

B

CARRY

formation after the power to the device is removed.

P R O B L E M S

Table 4.6 Pin Assignments for

Full Adder

Function Pin

A12

B15

Section 4.1 What Is a PLD?

4.1List some of the advantages of programmable logic over fixed-function logic.

4.2What does CPLD stand for? How is it different from the term PLD?

4.3List some types of PLDs other than CPLDs.

4.4Figure 4.48 shows a 4-to-1 multiplexer circuit. (The circuit switches one of four digital inputs to a single output, depending on the states of two “select inputs.”) State the number of 74HC type devices required to make this circuit. You may use the following devices: 74HC04 hex inverter; 74HC11 triple 3-input AND gate; 74HC4002 dual 4-input NOR gate (there are no 4-input OR devices available in the 74HC family). State how many devices are required to make two multiplexers.

Section 4.3 Graphic Design File

Section 4.4 Compiling MAX PLUS II Files

4.5Briefly describe the difference between a design file and a project in MAX PLUS II.

4.6State two ways to set the MAX PLUS II project to the current file.

4.7State the definitions of the following terms:

Problems 153

a.primitives

b.instance

4.8Use MAX PLUS II to create a Graphic Design File for the multiplexer circuit shown in Figure 4.48. Save the file as drive:\max2work\chapt4\problems\4to1mux.gdf. Assign pins as in Table 4.3. Set the project to the current file and compile.

4.9Figure 4.49 shows the circuit for a 4-channel demultiplexer, which switches a digital input to one of four outputs, depending in the states of two “select inputs.” Figure 4.49

Use MAX PLUS II to create a Graphic Design File for the demultiplexer circuit. Save the file as drive:\max2work\chapt4\problems\4ch_dmux.gdf. Assign pins as in Table 4.4. Set the project to the current file and compile.

4.10Repeat Problem 4.9 for the 2-bit equality comparator in Figure 4.50. This circuit generates a HIGH output when

the two 2-bit numbers A2A1 and B2B1 are equal. Save the file as drive:\max2work\chapt4\problems\eq_comp. gdf. Use the pin assignments in Table 4.5.

4.11Use MAX PLUS II to create a Graphic Design File for the half-adder circuit shown in Figure 4.51. The halfadder adds 2 bits to generate a sum and a carry output. Save the file as drive:\max2work\chapt4\problems\ halfadd.gdf. Create a default symbol for the file and compile, after setting the project to the current file. Do not assign pin numbers at this time.

4.12Use MAX PLUS II to create a Graphic Design File for the full adder circuit shown in Figure 4.52. The full adder combines two bits A and B, plus an input carry from a previous stage to generate a sum and a carry output.

Save the file as drive:\max2work\chapt4\problems\fulladd.gdf. Assign pin numbers as shown in Table 4.6. Set the project to the current file and compile.

4.13Examine the half adder circuit in Figure 4.51 and the full adder circuit in Figure 4.52. You should find two half adders in the full adder circuit. Use the half adder symbol you created in Problem 4.11 to create a full adder as a hierarchical design, consisting of two half adders and other logic. Save the file as drive:\max2work\chapt4\

O U T L I N E

5.1Decoders

5.2Encoders

5.3Multiplexers

5.4Demultiplexers

5.5Magnitude Comparators

5.6Parity Generators and Checkers

C H A P T E R O B J E C T I V E S

Upon successful completion of this chapter you will be able to:

•Design binary decoders using logic gates.

•Create decoder designs in MAX PLUS II, using Graphic Design Files or VHDL.

•Create MAX PLUS II simulation files to verify the operation of combinational circuits.

•Design BCD-to-seven-segment and hexadecimal-to-seven-segment decoders, including special features such as ripple blanking, using VHDL and Graphic Design Files in MAX PLUS II.

•Use MAX PLUS II Graphic Design Files and VHDL to generate the design for a 3-bit binary and a BCD priority encoder.

•Describe the circuit and operation of a simple multiplexer and program these functions in VHDL.

•Draw logic circuits for multiplexer applications, such as single-channel data selection, multibit data selection, waveform generation, and timedivision multiplexing (TDM).

•Describe demultiplexer circuits and program them using VHDL.

•Define the operation of a CMOS analog switch and its use in multiplexers and demultiplexers.

•Define the operation of a magnitude comparator and program its function in VHDL.

•Explain the use of parity as an error-checking system and draw simple parity-generation and checking circuits..

Anumber of standard combinational logic functions have been developed for digital circuits that represent many of the useful tasks that can be performed with digital

circuits.

Decoders detect the presence of particular binary states and can activate other circuits based on their input values or can convert an input code to a different output code. Encoders generate a binary or binary coded decimal (BCD) code corresponding to an active input.

Multiplexers and demultiplexers are used for data routing. They select a transmission path for incoming or outgoing data, based on a selection made by a set of binary-related inputs.

EXAMPLE 5.2

Application

A PC has two serial port cards called COM1 and COM2. Each card is activated when either one of two control inputs called IOR (Input/Output Read) and IOW (Input/Output Write) are active and a unique 10-bit address is present. IOR and IOW are active-LOW. The address is specified by bits A9 A8 A7 A6 A5 A4 A3 A2 A1 A0, which can be represented by three hexadecimal digits. The decoder outputs, COM1 Enable and COM2 Enable are both active-LOW.

The card for COM1 activates when (IOR OR IOW is LOW) AND the address is between 3F8H and 3FFH.

The card for COM2 activates when (IOR OR IOW is LOW) AND the address is between 2F8H and 2FFH.

Create a Graphic Design File in MAX PLUS II that implements the specified decoder.

Solution The lowest address that activates COM1 is

A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 3F8H 11 1111 1000

The highest COM1 address is

A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 3FFH 11 1111 1111