Файл: Digital design with CPLD applications and VHDL (R. Dueck, 2000).pdf

for the project will automatically be available. The Programmer dialog box will appear as in Figure 4.44. To download, click Program.

If the project was compiled for the FLEX10K device and the device is to be configured via a ByteBlaster, it must be configured via the

Multi-Device JTAG Chain available in the JTAG menu. Select the JTAG menu, shown in Figure 4.45, and choose

Multi-Device JTAG

Chain Setup.

In the Multi-Device JTAG Chain Setup window, shown in Figure 4.46, select the pulldown menu for the device name. Select

EPF10K20. Choose

Delete All to clear the box of any previous programming file names. Choose the Select Programming File button.

The Select Programming File dialog box will appear, as in Figure 4.47. Find and se-

drive:\max2work\maj_v

ote\maj_vote.sof. Click

OK. Choose the Add button in the JTAG setup box to add the SRAM Object File (sof) to the list. Choose the Detect JTAG Chain Info button to set up the hardware for programming. Choose

OK. Click the Configure button in the Programmer dialog box to download the binary information to the FLEX10K CPLD on the UP-1

board.

S U M M A R Y

1.A programmable logic device (PLD) is a digital device that is shipped blank and whose function is determined by the end user.

2.PLDs offer design flexibility, reduce board space and package count, and can be used to develop digital designs more quickly than fixed-function logic.

3.Some types of PLDs include PAL (programmable array logic), GAL (generic array logic), EPLD (erasable PLD), CPLD (complex PLD), FPGA (field-programmable gate array).

4.Complex PLDs (CPLDs) are devices with several programmable sections that are interconnected inside the chip.

5.PLD design and programming requires special software, such as Altera’s MAX PLUS II.

6.PLD designs can be entered by schematic capture (Graphic Design Files) or text-based languages, such as Altera Hardware Description Language (AHDL) and VHSIC Hardware Description Language (VHDL).

7.MAX PLUS II organizes PLD design files in a project. Since many operations in MAX PLUS II are performed on a project, you should set the project to the current file (File menu) whenever you change windows and make a modification to a design file.

8.Save your work every time you pause for thought.

9.A MAX PLUS II Graphic Design File (gdf) consists of graphical symbols of components that are interconnected by lines drawn between inputs and outputs of the components.

10.Circuit inputs and outputs in a gdf have special symbols. The input and output pins must be named, but need not be numbered in the first stages of a design.

ship between the inputs and outputs.

22.The entity declaration defines ports (inputs and outputs) and the type of each port (the range of values each port can have).

23.Some common types are BIT (0 or 1), STD_LOGIC (ninevalued standard logic), and INTEGER (whole numbers).

24.The STD_LOGIC type can take on any of the following values:

‘U’,— — Uninitialized

Glossary 149

11.The MAX PLUS II compiler translates the design information from a gdf or text file into binary data that can be downloaded into a PLD. For a MAX7000S, the compiler generates a Programmer Object File (pof) to program the device. For a FLEX10K, an SRAM Object File (sof) is generated to configure the device.

12.MAX7000S devices are nonvolatile; they stay programmed when the power is removed from the chip. FLEX10K devices are volatile; they lose their programming data when power is removed.

13.If a CPLD part number is not specified, the MAX PLUS II compiler will automatically select one. It is good practice to assign the part number of the device before compiling, as this can affect the accuracy of certain parts of the design process, such as simulation. The CPLDs on the Altera UP-1 board are EPM7128SLC84-7 and EPF10K20RC240-4.

14.Some useful compiler options are: Design Doctor (checks for good design practice), Timing SNF Extractor (compiles data required for timing simulations), and Smart Recompile (allows part of the compile process to be skipped if only part of a design has changed).

15.Compiler messages can be in green text (Info), blue text (Warning; possible problems, but not fatal), or red text (Error; fatal, compiling stops).

16.MAX PLUS II files can be arranged in a design hierarchy. That is, a MAX PLUS II file can contain components that are complete MAX PLUS II designs in and of themselves.

17.A file that contains other designs, but is not part of a higherlevel design, is called the top level of a hierarchy.

18.If the top level of a hierarchy is a gdf, lower-level designs are embedded in the gdf as default symbols that are created from the original design files of the components.

19.MAX PLUS II looks for default symbols in the present working directory, then in the directories specified as user libraries.

20.VHDL (VHSIC Hardware Description Language) is a textbased programming language used to model and program digital circuits.

21.Every VHDL file requires an entity declaration, which describes the external aspects of the design (inputs and outputs), and an architecture body, which describes the relation-

‘-’ — — Don’t care

25.STD_LOGIC is defined in a library called ieee. To use STD LOGIC, include the following two statements at the beginning of a file

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

26.A port in VHDL is an input or output. A signal is an internal connection, like a wire. A variable is a piece of working memory reserved by the VHDL file.

27.The simplest way to relate inputs and outputs in a VHDL design is with a concurrent signal assignment statement, which

has the form: x <= (a and b) or c; The port or signal on the left side is assigned the value of the logic expression on the right side. (Variables are assigned with a different operator.)

28.A port, signal, or variable can have a multiple-bit construction of type BIT_VECTOR or STD_LOGIC_VECTOR.

These structures are called vectors and can be referred to a separate elements (e.g., y(3) <= d(1) and d(0);) or as a group (e.g., y <= “1000”).

29.A selected signal assignment statement can act as a truth table in VHDL. It assigns alternative values to one or more outputs, depending on the alternative values on one or more inputs.

30.VHDL constructs and statements can be selected in generic form from a template menu in MAX PLUS II.

31.VHDL designs can be embedded in a gdf as default symbols.

32.Pin numbers must be assigned to a design before it can be downloaded to a CPLD. Pins can be assigned in the Pin/ Location/Chip dialog box (accessed by highlighting a pin symbol and right-clicking) or by editing the project’s Assignment and Configuration File (acf).

33.An Altera CPLD can be programmed directly from a PC parallel port via a ByteBlaster cable.

34.The ByteBlaster cable implements a programming interface specified by a standard (IEEE Std. 1149.1) of the Joint Test Action Group (JTAG).

35.A JTAG port is a 4-wire interface for loading test and programming information into one or more JTAG-compliant devices. It consists of an input (TDI), output (TDO), mode select (TMS), and clock (TCK).

Bit string literal A group of bits assigned to the elements of a vector, enclosed in double quotes (e.g., “001011”).

ByteBlaster An Altera ribbon cable and connector used to program or configure Altera CPLDs via the parallel port (LPT port) of an IBM PC or compatible.

Comment Explanatory text in a VHDL (or other computer language) file that is ignored by the computer at compile time.

Compile The process used by CPLD design software to interpret design information (such as a drawing or text file) and create required programming information for a CPLD.

Complex PLD (CPLD) A digital device consisting of several programmable sections with internal interconnections between the sections.

Concurrent Simultaneous.

Concurrent signal assignment A relationship between an input and output port or signal in which the output is changed as soon as there is a change in input. If the file has more than one concurrent signal assignment, they are all evaluated simultaneously.

Default symbol A graphical symbol that represents a PLD design as a block, showing only the design’s inputs and outputs. The symbol can be used as a component in any Graphic Design File.

Design entry The process of using software tools to describe the design requirements of a PLD. Design entry can be done by entering a schematic or a text file that describes the required digital function.

Download Program a PLD from a computer running PLD design and programming software.

Entity A VHDL structure that defines the inputs and outputs of a design.

Fitting Assigning internal PLD circuitry, as well as input and output pins, for a PLD design.

Graphic Design File (gdf) A PLD design file in which the digital design is entered as a schematic.

Hardware description language A computer language used to design digital circuits by entering text-based descriptions of the circuits.

G L O S S A R Y

AHDL (Altera Hardware Description Language) Altera’s proprietary text-entry design tool for PLDs.

Altera UP-1 Board A circuit board, part of Altera’s University Program Design Laboratory Package, containing two CPLDs and a number of input and output devices.

Architecture A VHDL structure than defines the relationship between input, output, and internal signals or variables in a design.

ASICs (application specific integrated circuits) Integrated circuits that are constructed for a specific design purpose. The term could refer to a PLD, although it usually means a customdesigned fixed function device.

Assignment and Configuration File (acf) A MAX PLUS II file that contains information about the configuration options for a project, including assigned device and pin numbers.

Hierarchical design A PLD design that is ordered in layers or levels. The highest level of design contains components that are themselves complete designs. These components may, in turn, have lower-level designs embedded within them.

ICR In-circuit reconfigurability. The ability of a PLD (such as a FLEX10K) to be configured without removing it from a circuit board.

IEEE Standard 1164 The standard which defines a variety of VHDL types and operations, including the STD_LOGIC and STD_LOGIC_VECTOR types.

ISP In-system programmability. The ability of a PLD (such as a MAX7000S) to be programmed without removing it from a circuit board.

JTAG Joint Test Action Group. A standards body that developed the format (called IEEE Std. 1149.1) for testing and programming devices while they are installed in a system.