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196

C H A P T E R

5 • Combinational Logic Functions

Telephone companies use TDM to maximize the use of their phone lines. Speech or

data is digitally encoded for transmission. Each speech or data channel becomes a multi-

plexer data input which shares time with all other channels on a single phone line. A

counter on the MUX selects the speech channels one after the other in a continuous se-

quence. The counter must switch the channels fast enough so that there is no apparent in-

terruption of the transmitted conversation or data stream.

EXAMPLE 5.10

Draw a diagram of a circuit that uses an 8-to-1 multiplexer to share one telephone line

among eight digitized speech channels.

Write a VHDL file for the multiplexer and create a simulation to show its operation.

Solution Figure 5.47 shows the required multiplexer circuit. Each channel is connected

to a data input and a 3-bit binary counter is connected to the select inputs.

Digitized speech channels

MUX

CH0

D0

D1

CH1

D2

D3

CH2

D4

Y

Telephone

CH3

D5

line

D6

CH4

D7

S0

S

2

S1

CH5

CH6

CH7

CTR DIV 8

CLOCK

Q2

Q1

Q0

FIGURE 5.47

Example 5.10

Time-Division Multiplexing of Telephone Channels

The VHDL code for the multiplexer is:

mux_8ch.vhd mux_8ch.scf

0);

d

: IN

BIT_VECTOR (7 downto 0);

y

: OUT

BIT);

END mux_8ch;

ARCHITECTURE a OF mux_8ch IS

BEGIN

—— Selected Signal Assignment MUX8: WITH sel SELECT

y <= d(0) WHEN “000”,

5.4 • Demultiplexers

197

d(1) WHEN “001”,

d(2) WHEN “010”,

d(3) WHEN “011”,

d(4) WHEN “100”,

d(5) WHEN “101”,

d(6) WHEN “110”,

d(7) WHEN “111”;

END a;

The simulation is shown in Figure 5.48. For clarity, digital data are present on the MUX inputs just before and after they are switched to the Y output. The output shows the channel data in sequence, starting with channel 0.

FIGURE 5.48

Simulation for an 8-bit Time-Division Multiplexer

SECTION 5.3 REVIEW PROBLEM

5.5What defines whether a multiplexer application is time-dependent or not? What additional component can be added to make a MUX application time-dependent?

5.4Demultiplexers

K E Y T E R M S

Demultiplexer A circuit that uses a binary decoder to direct a digital signal from

a single source to one of several destinations.

A demultiplexer performs the reverse function of a multiplexer. A multiplexer (MUX) directs one of several input signals to a single output; a demultiplexer (DMUX) directs a single input signal to one of several outputs. In both cases, the selected input or output is chosen by the state of an internal decoder.

Figure 5.49 shows the logic circuit for a 1-to-4 demultiplexer. Compare this to Figure 5.4, a 4-output decoder. This circuits are the same except that the active-LOW enable input has been changed to an active-HIGH data input. The circuit in Figure 5.49 could still be used as a decoder, except that its enable input would be active-HIGH.

198 C H A P T E R 5 • Combinational Logic Functions

S0

S1

D

Y0

Y1

Y2

Y3

FIGURE 5.49

4-bit Decoder/Demultiplexer

Each AND gate in the demultiplexer enables or inhibits the signal output according to the state of the select inputs, thus directing the data to one of the output lines. For instance, S1S0 10 directs incoming digital data to output Y2.

S1

Y0

S1

Y0

Binary

Channel

input

S0

select

S0

Y1

Y1

Vcc

Y2

Y2

D

Y3

Signal

D

Y3

a. Decoder

b. Demultiplexer

FIGURE 5.50

Same Device Used as a Decoder or Demultiplexer

Figure 5.50 illustrates the use of a single device as either a decoder or a demultiplexer. In Figure 5.50a, input D is tied HIGH. When an output is selected by S1 and S0, it goes HIGH, acting as a decoder with active-HIGH outputs. In Figure 5.50b, D acts as a demultiplexer data input. The data are directed to the output selected by S1 and S0.

N O T E

Since a single device can be used either way, this implies that any of the VHDL binary decoder designs used in this chapter can also be used as demultiplexers.

A decoder/demultiplexer can have active-LOW outputs, but only if the D input is also active-LOW. This is important because the demultiplexer data must be inverted twice to retain its original logic values.

Demultiplexing a TDM Signal

In Example 5.10, we saw how a multiplexer could be used to send 8 digital channels across a single line, multiplexed over time. Obviously, such a system is not of much value if the signals cannot be sorted out at the receiving end. The received digital data must be demultiplexed and sent to their appropriate destinations.

5.4

•

Demultiplexers

199

The process is the reverse of multiplexing; data are sent to an output selected by a counter

at the DMUX select inputs. (We assume that the counters at the MUX and DMUX select in-

puts are somehow synchronized or possibly, if located close together, are the same counter.)

EXAMPLE 5.11

Draw a demultiplexing circuit that will take the multiplexed output of the circuit in Fig-

ure 5.47 and distribute it to 8 different local telephone circuits. Write a VHDL file for the

demultiplexer and create a simulation file that shows its operation. Use active-LOW out-

puts for the demultiplexer. How does this affect the outputs when they are not transmit-

ting data?

Solution Figure 5.51 shows the original multiplexing circuit connecting to the new de-

multiplexing circuit. The diagram indicates that the two sides of the circuit are separated

by some distance. The clock is shared between both sides of the circuit, but is generated

on the MUX side. Both sides share a common ground. Each side of the circuit has its own

3-bit counter.

FIGURE 5.51

Example 5.11

MUX

DMUX

Time-Division Multiplexing and

CH0

D0

Demultiplexing

Y0

CH0

D1

Y1

CH1

CH1

D2

Y2

D3

Y

D

CH2

CH2

D

Y3

CH3

4

Y

CH3

D5

4

CH4

D6

S2

Y5

CH5

CH4

D7

S

S

1

Y6

CH6

S2 S1

0

S0

Y7

CH7

CH5

CTR DIV 8

CH6

Q

Q

2

Q

1

Q

0

2

CH7

Q1

Q0

CTR DIV 8

CLOCK

The VHDL code for the demultiplexer is as follows. (This is the same implementation as a 3-line-to-8-line decoder with an enable input.)

—— dmux8.vhd

—— 1-to-8 demultiplexer/decoder

dmux8.vhd

—— Decoder: set d to ‘0’; outputs are activated by

dmux8.scf

——binary combination of s.

——Demultiplexer: apply data stream to d; data directed to

——y output with subscript same as value of s.

——Outputs and d are active-LOW. DMUX data are inverted twice

——to keep them true.

200

C H A P T E R 5 • Combinational Logic Functions

ENTITY dmux8 IS

PORT(

s

: IN

INTEGER Range 0 to 7;

d

: IN

BIT;

y

: OUT

BIT_VECTOR (0 to 7));

END dmux8;

ARCHITECTURE a OF dmux8 IS

SIGNAL output : BIT_VECTOR (0 to 7);

BEGIN

PROCESS (d, s)

BEGIN

IF

(d ‘1’) THEN

output <= “11111111”;

ELSE

CASE s IS

WHEN 0 =>

output

<=

“01111111”;

WHEN 1 =>

output

<=

“10111111”;

WHEN 2 =>

output

<=

“11011111”;

WHEN 3 =>

output

<=

“11101111”;

WHEN 4 =>

output

<=

“11110111”;

WHEN 5 =>

output

<=

“11111011”;

WHEN 6 =>

output

<=

“11111101”;

WHEN 7 =>

output

<=

“11111110”;

WHEN OTHERS => output <=

“11111111”;

END

CASE;

END

IF;

y

<=

output;

END PROCESS;

END a;

www.electronictech.com

The simulation, shown in Figure 5.52, has as its input data the output of the original

MUX simulation in Figure 5.48. Data are distributed to the outputs in sequence. Compare

the DMUX output data to the MUX input data in Figure 5.48.

FIGURE 5.52

Example 5.11

Demultiplexer Simulation

Note that idle channels sit HIGH. This is opposite from the status of the idle MUX lines and may affect circuit operation. If so, a DMUX with active-HIGH outputs and ac-

tive-HIGH enable should be used.

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