Файл: Digital design with CPLD applications and VHDL (R. Dueck, 2000).pdf

Сделать презентацию

Скачать файл (8,59Мб)

Заказать решение

ВУЗ: Не указан

Категория: Не указан

Дисциплина: Не указана

Добавлен: 13.06.2025

Просмотров: 8140

Скачиваний: 6

ВНИМАНИЕ! Если данный файл нарушает Ваши авторские права, то обязательно сообщите нам.

5.5 • Magnitude Comparators

207

FIGURE 5.62

Simulation for a 2-bit Magnitude Comparator

The following code for a 4-bit comparator illustrates a much more efﬁcient method. Since VHDL allows inputs to be represented as integers, we can deﬁne the required size of inputs A and B and compare them using IF statements. For every comparison, we assign an output vector consisting of bits for ALTB, AEQB, and AGTB one of the values 110, 101, or 011, for active-LOW outputs. For example, if A 12 and B 9, then the output vector would be 011 (i.e., A B). An active-LOW output will illuminate a LOW-sense LED,

compare4.vhd

compare4.scf

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY compare4 IS
PORT(
a, b	: IN	INTEGER RANGE 0 TO 15;
agtb, aeqb, altb : OUT		STD_LOGIC);
END compare4;

ARCHITECTURE a OF compare4 IS

SIGNAL compare : STD_LOGIC_VECTOR (2 downto 0);

BEGIN
PROCESS (a,b)
BEGIN
IF a<b THEN
compare		<=	“110”;
ELSIF a=b THEN
compare		<=	“101”;
ELSIF a>b THEN
compare		<=	“011”;
ELSE
compare		<=	“111”;
END IF;
agtb	<=	compare(2);
aeqb	<=	compare(1);
altb	<=	compare(0);

END PROCESS;

END a;

The beauty of this method is that the number of input bits can be changed by modifying one number: the range of the INTEGER-type input. For example, a 12-bit comparator is identical to the 4-bit comparator in the previous VHDL code, except that the inputs have a range of 0 to 4095 ( 212 1). Using this method, we can program an EPM7128S CPLD

C H A P T E R 5 • Combinational Logic Functions

with a comparator up to 28 bits wide (range of 0 to 268,435,455). If we do, however, there is no room for anything else.

5.14Write a VHDL ﬁle that uses IF statements to compare two 8-bit numbers A and B. The design should have outputs for AEQB, ALTB, and AGTB.

Solution

—— compare8.vhd
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY compare8 IS
PORT(
a, b	: IN	INTEGER RANGE 0 TO 255;

compare8.vhd

ARCHITECTURE a OF compare8 IS

SIGNAL compare : STD_LOGIC_VECTOR (2 downto 0);

BEGIN
PROCESS (a,b)
BEGIN
IF a<b THEN
	compare	<=	“110”;
ELSIF a=b THEN
	compare	<=	“101”;
ELSIF a>b THEN
	compare	<=	“011”;
ELSE
	compare	<=	“111”;
END IF;
agtb	<= compare(2);
aeqb	<= compare(1);
altb	<= compare(0);

END PROCESS;

END a;

5.6 Parity Generators and Checkers

K E Y T E R M S

Parity A system that checks for errors in a multi-bit binary number by counting the number of 1s.

Even parity An error-checking system that requires a binary number to have an even number of 1s.

Odd parity An error-checking system that requires a binary number to have an odd number of 1s.

Parity bit A bit appended to a binary number to make the number of 1s even or odd, depending on the type of parity.

When data are transmitted from one device to another, it is necessary to have a system of checking for errors in transmission. These errors, which appear as incorrect bits, occur as a result of electrical limitations such as line capacitance or induced noise.

5.6 • Parity Generators and Checkers

209

FIGURE 5.63

Parity Error Checking

Parity error checking is a way of encoding information about the correctness of data before they are transmitted. The data can then be veriﬁed at the system’s receiving end. Figure 5.63 shows a block diagram of a parity error-checking system.

		The parity generator in Figure 5.63 examines the outgoing data and adds a bit called
	the parity bit that makes the number of 1s in the transmitted data odd or even, depending
	on the type of parity. Data with EVEN parity have an even number of 1s, including the
	parity bit, and data with ODD parity have an odd number of 1s.
		The data receiver “knows” whether to expect EVEN or ODD parity. If the incoming
	number of 1s matches the expected parity, the parity checker responds by indicating that
	correct data have been received. Otherwise, the parity checker indicates an error.

EXAMPLE 5.16	Data are transmitted from a PC serial port to a modem in groups of 7 data bits plus a parity
	bit. What should the parity bit, P, be for each of the following data if the parity is EVEN?
	If the parity is ODD?
	a.	0110110
	b.	1000000
	c.	0010101

Solution

a. 0110110 Four 1s in data. (4 is an even number.) EVEN parity: P 0

ODD parity: P 1

b. 1000000 One 1 in data. (1 is an odd number.) EVEN parity: P 1

ODD parity: P 0

c. 0010101 Three 1s in data. (3 is an odd number.) EVEN parity: P 1

ODD parity: P 0

FIGURE 5.64

Exclusive OR Gate

An Exclusive OR gate can be used as a parity generator or a parity checker. Figure 5.64 shows the gate, and Table 5.12 is the XOR truth table. Notice that each line of the XOR truth table has an even number of 1s if we include the output column.

Figure 5.65 shows the block diagram of a circuit that will generate an EVEN parity bit from 2 data bits, A and B, and transmit the three bits one after the other, that is, serially, to a data receiver.

210 C H A P T E R 5 • Combinational Logic Functions

Table 5.12 Exclusive

OR Truth Table

A	B	A B

0	0	0
0	1	1
1	0	1
1	1	0

FIGURE 5.65

Even Parity Generation

FIGURE 5.66

Even Parity Checking

	Figure 5.66 shows a parity checker for the parity generator in Figure 5.65. Data are re-
	ceived serially, but read in parallel. The parity bit is re-created from the received values of
	A and B, and then compared to the received value of P to give an error indication, P . If P
	and A B are the same, then P 0 and the transmission is correct. If P and A B are
	different, then P 1 and there has been an error in transmission.

EXAMPLE 5.17	The following data and parity bits are transmitted four times: ABP 101.
	1. State the type of parity used.
	2. The transmission line over which the data are transmitted is particularly noisy and the
	data arrive differently each time as follows:
	a. ABP 101
	b. ABP 100
	c. ABP 111
	d. ABP 110
	Indicate the output P of the parity checker in Figure 5.66 for each case and state what
	the output means.