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5.3 • Multiplexers

185

CD: hi_pri10.scf

SECTION 5.2 REVIEW PROBLEM

S0

S1

D0

D1

D2

D3

FIGURE 5.34

4-to-1 Multiplexer

5.4State the main limitation of the 3-bit binary encoder shown in Figure 5.29. How can the encoder be modified to overcome this limitation?

5.3Multiplexers

K E Y T E R M S

Multiplexer A circuit that directs one of several digital signals to a single output, depending on the states of several select inputs.

Data inputs The multiplexer inputs that feed a digital signal to the output when selected.

Select inputs The multiplexer inputs that select a digital input channel.

Double-subscript notation A naming convention where two or more numerically related groups of signals are named using two subscript numerals. Generally, the first digit refers to a group of signals and the second to an element of a group. (e.g., X03 represents element 3 of group 0 for a set of signal groups, X.)

A multiplexer (abbreviated MUX) is a device for switching one of several digital signals to an output, under the control of another set of binary inputs. The inputs to be switched are called the data inputs; those that determine which signal is directed to the output are called the select inputs.

INPUT

INPUT

NOT

NOT

INPUT

AND3

INPUT

AND3

OR4

OUTPUT

INPUT

AND3

Y

INPUT

AND3

Figure 5.34 shows the logic circuit for a 4-to-1 multiplexer, with data inputs labelled D0 to D3 and the select inputs labelled S0 and S1. By examining the circuit, we can see that the 4-to-1 MUX is described by the following Boolean equation:

Y D0S1S0 D1S1S0 D2S1S0 D3S1S0

186 C H A P T E R 5 • Combinational Logic Functions

Table 5.8

4-to-1 MUX

Truth Table

S1

S0

Y

0

0

D0

0

1

D1

1

0

D2

1

1

D3

For any given combination of S1S0, only one of the above four product terms will be enabled. For example, when S1S0 10, the equation evaluates to:

Y (D0 0) (D1 0) (D2 1) (D3 0) D2

The MUX equation can be described by a truth table as in Table 5.8. The subscript of the selected data input is the decimal equivalent of the binary combination S1S0.

Figure 5.35 shows two symbols used for a 4-to-1 multiplexer. The first symbol shows the data and select inputs as individual lines. The second symbol shows the data inputs as a single 4-bit bus line and the select inputs as a 2-bit bus.

D0

4

D1

Y

D

Y

D2

D3

2

S1S0

S

a. 4-to-1 MUX symbol

b. 4-to-1 MUX symbol

showing individual lines

showing bus lines

FIGURE 5.35

Multiplexer Symbols

In general, a multiplexer with n select inputs will have m 2n data inputs. Thus, other common multiplexer sizes are 8-to-1 (for 3 select inputs) and 16-to-1 (for 4 select inputs). Data inputs can also be multiple-bit busses, as in Figure 5.36. The slash through a thick data line and the number 4 above the line indicate that it represents four related data signals. In this device, the select inputs switch groups of data inputs, as shown in the truth table in Table 5.9.

4

Table 5.9

Truth Table for a

D0

4-to-1 4-bit Bus MUX

4

4

D1

S1

S0

Y3 Y2 Y1 Y0

Y

4

D2

0

0

D03D02D01D00

4

0

1

D13D12D11D10

D3

1

0

D23D22D21D20

1

1

D33D32D31D30

S1S0

FIGURE 5.36

4-to-1 4-bit Bus Multiplexer

The naming convention shown in Table 5.9, known as double-subscript notation, is used frequently for identifying variables that are bundled in numerically related groups, the elements of which are themselves numbered. The first subscript identifies the group that a variable belongs to; the second subscript indicates which element of the group a variable represents.

Multiplexing of Time-Varying Signals

We can observe the function of a multiplexer by using time-varying waveforms, such as a series of digital pulses. If we apply a different digital signal to each data input, and step the

mux4.vhd

mux4.scf

5.3 • Multiplexers

187

select inputs through an increasing binary sequence, we can see the different input waveforms appear at the output in a predictable sequence, as shown by the simulation waveforms in Figure 5.37. The frequencies shown in the simulation were chosen to make as great a contrast as possible between adjacent inputs so that the different selected inputs could easily be seen.

FIGURE 5.37

Simulation Waveforms for a 4-to-1 MUX

In Figure 5.37, we initially see the D0 waveform appearing at the Y output when S1S0 00, followed in sequence by the D1, D2, and D3 waveforms when S1S0 01, 10, and 11, respectively. (The S1S0 input combination is shown as a single hexadecimal value between 0 and 3, labelled S[1..0].)

This simulation can be created in the MAX PLUS II simulator by defining a base clock pulse length (e.g., 40 ns) and assigning that to one of the inputs (D1 in this case). Other input waveforms are set to periods of 2, 4, and 8 times the base waveform period (for D3, D2, and D0, respectively). The select input count waveforms are set to allow three cycles of the longest waveform (D0) to appear at Y when selected.

VHDL Implementation of Multiplexers

A multiplexer can be represented in MAX PLUS II as a Graphic Design File, similar to the diagram of Figure 5.34, or in a hardware description language such as VHDL.

Several different VHDL constructs can be used to define a multiplexer. We can use a concurrent signal assignment statement, a selected signal assignment statement, or a CASE statement within a PROCESS. We will briefly look at each form for a 4-to-1 multiplexer. Later, you will be required to extend these constructs to larger multiplexer circuits.

Concurrent Signal Assignment

Recall that the concurrent signal assignment statement takes the form:

__signal <= __expression;

We can use this to encode the Boolean expression that describes a 4-to-1 MUX. The VHDL file that incorporates this statement is as follows.

signals (d0 to d3) to output,

——depending on status of select bits (s1, s0).

188

C H A P T E R 5 • Combinational Logic Functions

ENTITY mux4 IS

PORT(

d0, d1, d2, d3 : IN

BIT;

s

: IN

BIT_VECTOR (1 downto 0);

y

: OUT

BIT);

END mux4;

ARCHITECTURE mux4to1 OF mux4 IS

BEGIN

——Concurrent Signal Assignment

y<= ((not s(1)) and (not s(0)) and d0)

or ((not

s(1)) and (

s(0)) and d1)

or ((

s(1)) and (not

s(0)) and

d2)

or ((

s(1)) and (

s(0)) and

d3);

END mux4to1;

While the concurrent signal assignment is fairly easy to use, it becomes cumbersome for larger multiplexers, such as 8-to-1 or greater.

The entity declaration will be identical for the other VHDL examples. The only change we will make will be to replace the concurrent signal assignment in the architecture body with some other VHDL construct.

Selected Signal Assignment Statement

This construct has the following form (the label is optional):

__label:

WITH __expression SELECT

__signal <=

__expression WHEN __constant_value,

__expression WHEN __constant_value,

__expression WHEN __constant_value,

__expression WHEN __constant_value;

The 4-to-1 MUX can be described in VHDL as follows, using a selected signal assignment:

mux4sel IS

mux4sel.vhd

d0, d1, d2, d3 : IN

BIT;

s

: IN

BIT_VECTOR (1 downto 0);

y

: OUT

BIT);

END mux4sel;

ARCHITECTURE mux4to1 OF mux4sel IS

BEGIN

M:WITH s SELECT

y <= d0 WHEN “00”,

d1

WHEN “01”,

d2

WHEN

“10”,

d3

WHEN

“11”;

END mux4to1;

The selected signal assignment evaluates the expression in the WITH clause (in this case, the 2-bit vector, s) and, depending on its value, selects an expression to assign to y. Thus, if s1s0 00, y d0. If s1s0 01, then y d1, and so on for the remaining values of s1s0.

5.3 • Multiplexers

189

CASE Statement within a PROCESS

In our MUX example, we could use a CASE statement as follows:

mux4case.vhd

s

: IN

BIT_VECTOR (1 downto 0);

y

: OUT

BIT);

END mux4case;

ARCHITECTURE mux4to1 OF mux4case IS

BEGIN

——CASE statement within a PROCESS

——Monitor select inputs and execute if they change PROCESS (s)

BEGIN

CASE s IS

WHEN “00”

=>

y

<=

d0;

WHEN “01”

=>

y

<=

d1;

WHEN “10”

=>

y

<=

d2;

WHEN “11”

=>

y

<=

d3;

WHEN others

=>

y

<=

‘0’;

END CASE;

END PROCESS;

END mux4to1;

If the select inputs change, the PROCESS statements are executed. The CASE statement evaluates the select input vector, s, and chooses a signal assignment based on its value. It is good design practice to include a default case (the “others” clause) even when there are no obvious other cases. A default case is essential when using STD_LOGIC types rather than BIT types, as ‘0’ and ‘1’ values do not cover all possible cases for STD LOGIC signals. (Recall from Chapter 4 that STD_LOGIC is a nine-valued logic type, incorporating such things as “Don’t Care” (‘-’), “Unknown” (‘X’), and “High Impedance” (‘Z’), as well as ‘0’ and ‘1’.)

Multiplexer Applications

Multiplexers are used for a variety of applications, including selection of one data stream

out of several choices, switching multiple-bit data from several channels to one multiple-

bit output, sharing data on one output over time, and generating bit patterns or waveforms.

Single-Channel Data Selection

The simplest way to use a multiplexer is to switch the select inputs manually in order to di-

rect one data source to the MUX output. Example 5.6 shows a pair of single-pole single-

throw (SPST) switches supplying the select input logic for this type of application.

5.6

Figure 5.38 shows a digital audio switching system. The system shown can select a signal

from one of four sources (compact disc (CD) players, labelled CD0 to CD3) and direct it to

a digital signal processor (DSP) at its output. We assume we have direct access to the au-

dio signals in digital form.

Make a table listing which digital audio source in Figure 5.38 is routed to the DSP for

each combination of the multiplexer select inputs, S1 and S0.

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