Файл: Digital design with CPLD applications and VHDL (R. Dueck, 2000).pdf

how the compiler deals the change in output active level.

5.9Create a MAX PLUS II simulation file for the decoder in Problem 5.8.

5.10Write a VHDL file for a 3-line-to-8-line decoder with ac- tive-LOW outputs and an active-LOW enable input.

5.11Create a MAX PLUS II simulation file for the decoder in Problem 5.10.

5.12Write a truth table for a hexadecimal-to-seven-segment decoder for a common anode display. Use the digit patterns of Figure 5.26 as a model.

5.13Use the truth table derived in Problem 5.12 to derive the Boolean equations for each segment driver. Simplify the equations as much as possible, using any convenient method.

FIGURE 5.72

Problem 5.17

BCD Priority Encoder

Problems 217

5.14Write a VHDL file for the hexadecimal-to-seven-segment decoder described in Problem 5.12.

5.15Modify the VHDL file for the hexadecimal-to-seven- segment decoder from Problem 5.14 to add a rippleblanking feature.

5.16Draw a diagram consisting of four seven-segment displays, each driven by a BCD-to-seven-segment decoder with ripple blanking. The circuit should be configured to

suppress all leading zeros. Show the displayed digits and

RBO/RBI logic levels for each of the following displayed values: 100, 217, 1024.

Section 5.2 Encoders

5.17Figure 5.72 shows a BCD priority encoder with three different sets of inputs. Determine the resulting output code for each input combination. Inputs and outputs are active HIGH.

5.18 Derive the Boolean equations for the outputs of a BCD priority encoder, based on the encoding principle stated in Section 5.2. Show all work.

5.19Create a Graphic Design File in MAX PLUS II for a BCD priority encoder, based on the equations in Problem 5.18. Also generate a simulation for this function.

5.20Write a VHDL file that implements the function of a BCD priority encoder. Create a simulation file for this function. Write the Boolean equations of the encoder, as shown in the encoder’s report file. State how the equations from the report file compare to the equations you derived in Problem 5.18.

5.21Write a VHDL file that implements the function of a 4-bit binary priority encoder. Create a simulation file for this function.

Section 5.3 Multiplexers

5.22Make a table listing which digital audio source in Figure 5.73 is routed to output Y for each combination of

the multiplexer select inputs. (CD compact disc; DAT digital audio tape.)

5.23Draw symbols for an 8-to-1 and a 16-to-1 multiplexer. Write the truth table for each multiplexer, showing which data input is selected for every binary combination of the select inputs.

5.24Make a Graphic Design File in MAX PLUS II for an 8- to-1 multiplexer circuit. Also create a simulation that shows the operation of the device.

5.25Write the Boolean expression describing an 8-to-1 multi-

plexer. Evaluate the equation for the case where input D5 is selected.

5.26Draw the symbol for a quadruple 8-to-1 multiplexer (i.e., a MUX with eight switched groups of 4 bits each). Write the truth table for this device, showing which data inputs are selected for every binary combination of the select inputs. Use double-subscript notation.

5.27Write a VHDL file for the quadruple 8-to-1 multiplexer in Problem 5.26. Create a MAX PLUS II simulation for the design to verify its operation.

5.28Draw the symbol for an octal 4-to-1 multiplexer (i.e., a MUX with four switched groups of 8 bits each). Write the truth table for this device, showing which data inputs are selected for every binary combination of the select inputs. Use double-subscript notation.

5.29Write a VHDL file for the octal 4-to-1 multiplexer in the Problem 5.28. Create a MAX PLUS II simulation for the design to verify its operation. Write its Boolean equations from the project report file.

5.30Write a VHDL file for an 8-to-1 multiplexer using a concurrent signal assignment statement to encode the multiplexer’s Boolean equation directly. Would this be a good method for encoding a larger device, such as a 16-to-1 multiplexer? Explain your answer.

5.31Write a VHDL file for an 8-to-1 multiplexer using a selected signal assignment statement. Would this be a good method for encoding a larger device, such as a 16-to-1 multiplexer? Explain your answer.

5.32Write a VHDL file for a 16-to-1 multiplexer using the method you believe to be most efficient.

5.33Draw the circuit of a programmable waveform generator based on an 8-to-1 multiplexer. Draw a timing diagram of this circuit for the following input data:

a.D7 D6 D5 D4 D3 D2 D1 D0 01100101

b.D7 D6 D5 D4 D3 D2 D1 D0 01010101

5.34The data pattern in Problem 5.34b generates a symmetrical 12 kHz waveform. Write the data patterns required to produce a 6 kHz waveform and a 3 kHz waveform at the output of a MUX-based programmable waveform generator.

Section 5.4 Demultiplexers

5.35Make a Graphic Design File in MAX PLUS II for a 1-to-4 demultiplexer circuit with active-LOW outputs and an active-LOW enable input. Create a simulation that shows how this device can be used as a demultiplexer or decoder.

5.36Make a Graphic Design File in MAX PLUS II for a 1-to-8 demultiplexer circuit with active-HIGH outputs. Create a simulation that shows the operation of the device.

5.37Write a VHDL file that implements the function of a 1-to- 16 demultiplexer.

5.38Briefly state what characteristics of an analog switch make it suitable for transmitting analog signals.

5.39Draw a diagram showing how eight analog switches can be connected to a decoder to form an 8-channel MUX/DMUX circuit. Briefly explain why the same circuit can be used as a multiplexer or as a demultiplexer.

5.40Draw a circuit showing how a 74HC4052 dual 4-channel analog MUX/DMUX can be used to multiplex four transmitted digital audio channels onto a phone line and demultiplex four received audio channels from another phone line.

Section 5.5 Magnitude Comparators

5.41Briefly explain the operation of the ALTB portion of the 2-bit magnitude comparator shown in Figure 5.58.

5.42Draw the ALTB portion of a 4-bit magnitude comparator as a Graphic Design File in MAX PLUS II. Create a simulation for the circuit and briefly explain its operation.

5.43Use MAX PLUS II to create a 3-bit magnitude comparator that has outputs for AEQB, AGTB, and ALTB functions. Create a simulation that shows the operation of this circuit.

5.44Write the Boolean expressions for the AEQB, ALTB, and AGTB outputs of a 6-bit magnitude comparator.

5.45Write a VHDL file that implements the functions A B, A B and A B for two 16-bit numbers.

5.46Write a VHDL file that implements the following six comparison functions in a single device for two 4-bit in-

puts A and B: A B, A B, A B, A B, A B, and A B. Make the outputs indicate active-LOW.

5.47Create a simulation that verifies the operation of the sixfunction comparator in Problem 5.46.

Section 5.6 Parity Generators and Checkers

5.48What parity bit, P, should be added to the following data if the parity is EVEN? If the parity is ODD?

a.1111100

b.1010110

c.0001101

5.49The following data are transmitted in a serial communication system (P is the parity bit). What parity is being used in each case?

a.ABCDEFGHP 010000101

b.ABCDEFGHP 011000101

c.ABCDP 01101

d.ABCDEP 101011

e.ABCDEP 111011

5.50The data ABCDEFGHP 110001100 are transmitted in a serial communication system. Give the output P of a receiver parity checker for the following received data. State the meaning of the output P for each case.

a.ABCDEFGHP 110101100

b.ABCDEFGHP 110001101

c.ABCDEFGHP 110001100

d.ABCDEFGHP 110010100

5.51Use MAX PLUS II to create a Graphic Design File for a 5-bit parity generator with a switchable EVEN/ODD output. Create a simulation file to show the operation of the device.

5.52Use MAX PLUS II to create a Graphic Design File for a 5-bit parity checker corresponding to the parity generator in Problem 5.51. Create a simulation file to show the operation of the device.

FIGURE 5.74

Decoders

Section 5.1b

5.2 A decoder with 16 outputs requires 4 inputs. A decoder with 32 outputs requires 5 inputs.

Section 5.1c

5.3 Trailing zeros could logically be suppressed after a decimal point or if there are digits displaying a power-of-ten exponent (e.g., 455. or 4.55 02), that is, if the zeros are nonsignificant. The zeros should be displayed if they set the location of the decimal point (e.g., 450).

Section 5.3

5.5 A multiplexer application is time-dependent if its channels are selected in a repeating sequence. This can be accomplished by connecting a binary counter to the select inputs of the multiplexer.

Section 5.6

5.6 Parts a and c are certainly incorrect because each has an even number of 1s. Items b, d, and e could have an even number of errors, which is undetectable by parity checking.

O U T L I N E

6.1Digital Arithmetic

6.2Representing Signed Binary Numbers

6.3Signed Binary Arithmetic

6.4Hexadecimal Arithmetic

6.5Numeric and Alphanumeric Codes

6.6Binary Adders and Subtractors

6.7BCD Adders

6.8Carry Generation in MAX PLUS II

C H A P T E R O B J E C T I V E S

Upon successful completion of this chapter, you will be able to:

•Add or subtract two unsigned binary numbers.

•Write a signed binary number in true-magnitude, 1’s complement, or 2’s complement form.

•Add or subtract two signed binary numbers.

•Explain the concept of overflow.

•Calculate the maximum sum or difference of two signed binary numbers that will not result in an overflow.

•Add or subtract two hexadecimal numbers.

•Write decimal numbers in BCD codes, such as 8421 (Natural BCD) and Excess-3 code.

•Construct a Gray code sequence.

•Use the ASCII table to convert alphanumeric characters to hexadecimal or binary numbers and vice versa.

•Derive the logic gate circuits for full and half adders, given their truth tables.

•Demonstrate the use of full and half adder circuits in arithmetic and other applications.

•Add and subtract n-bit binary numbers, using parallel binary adders and logic gates.

•Explain the difference between ripple carry and parallel carry.

•Design a circuit to detect sign-bit overflow in a parallel adder.

•Draw circuits to perform BCD arithmetic and explain their operation.

•Use VHDL to program CPLD devices to perform various arithmetic functions, such as parallel adders, overflow detectors, and 1’s complementers.

There are two ways of performing binary arithmetic: with unsigned binary numbers or with signed binary numbers. Signed binary numbers incorporate a bit defining the sign of a number; unsigned binary numbers do not. Several ways of writing signed binary num-

bers are true-magnitude form, which maintains the magnitude of the number in binary value, and 1’s complement and 2’s complement forms, which modify the magnitude but are more suited to digital circuitry.