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240

C H A P T E R 6 • Digital Arithmetic and Arithmetic Circuits

FIGURE 6.2

Half Adder Circuit

FIGURE 6.3

Full Adder

Table 6.7 Full Adder Truth

Table

A

B

CIN

COUT

0

0

0

0

0

0

0

1

0

1

0

1

0

0

1

0

1

1

1

0

1

0

0

0

1

1

0

1

1

0

1

1

0

1

0

1

1

1

1

1

The corresponding logic circuit is shown in Figure 6.2.

The half adder circuit cannot account for an input carry, that is, a carry from a lowerorder 1-bit addition. A full adder, shown in Figure 6.3, can add two 1-bit numbers and accept a carry bit from a previous adder stage. Operation of the full adder is based on the following sums:

0 0 0 00

0 0 1 01

0 1 1 10

1 1 1 11

Designating the left side of the above equalities as circuit inputs A, B, and CIN and the right side as outputs COUT and , we can make the truth table in Table 6.7. (The second and third of the above sums each account for three lines in the full adder truth table.)

The unsimplified Boolean expressions for the outputs are:

COUT A B CIN A B CIN A B CIN A B CIN

A B CIN A B CIN A B CIN A B CIN

There are a couple of ways to simplify these expressions.

Karnaugh Map Method

Since we have expressions for and COUT in sum-of-products form, let us try to use the Karnaugh maps in Figure 6.4 to simplify them. The expression for doesn’t reduce at all.

The simplified expression for COUT is:

COUT A B A CIN B CIN

FIGURE 6.4

K-Maps for a Full Adder

The corresponding logic circuits for and COUT, shown in Figure 6.5, don’t give us much of a simplification.

Boolean Algebra Method

The simplest circuit for COUT and involves the Exclusive OR function, which we cannot derive from K-map groupings. This can be shown by Boolean algebra, as follows:

COUT A B CIN A B CIN A B CIN A B CIN

(A B A B)CIN A B (CIN CIN)

(A B) CIN A B

6.6 • Binary Adders and Subtractors

241

FIGURE 6.5

Full Adder from K-Map Simplification

(A B AB) CIN (A B A B) CIN

(A B) CIN (A B) CIN

Let x A B

x CIN x CIN

x CIN

(A B) CIN

The simplified expressions are as follows:

N O T E

COUT (A B) CIN A B

(A B) CIN

Figure 6.6 shows the logic circuit derived from these equations. If you refer back to the half adder circuit in Figure 6.2, you will see that the full adder can be constructed from two half adders and an OR gate, as shown in Figure 6.7.

FIGURE 6.6

Full Adder from Logic Gates

242

C H A P T E R 6 • Digital Arithmetic and Arithmetic Circuits

Half Adder

Half Adder

FIGURE 6.7

Full Adder From Two Half Adders

EXAMPLE 6.18

FIGURE 6.8

Example 6.18

Full Adder

Evaluate the Boolean expression for and COUT of the full adder in Figure 6.8 for the following input values. What is the binary value of the outputs in each case?

a.A 0, B 0, CIN 1

b.A 1, B 0, CIN 0

c.A 1, B 0, CIN 1

d.A 1, B 1, CIN 0

SOLUTION The output of a full adder for any set of inputs is simply given by COUT A B CIN. For each of the stated sets of inputs:

a.COUT A B CIN 0 0 1 01

b.COUT A B CIN 1 0 0 01

c.COUT A B CIN 1 0 1 10

d.COUT A B CIN 1 1 0 10

We can verify each of these sums algebraically by plugging the specified inputs into the full adder Boolean equations:

COUT (A B) CIN A B

(A B) CIN

a.COUT (0 0) 1 0 0

0 1 0

0 0 0

(0 0) 1

0 1 1

(Binary equivalent: COUT 01)

b.COUT (1 0) 0 1 0

1 0 0

0 0 0

(1 0) 0

1 0 1

(Binary equivalent: COUT 01)

c.COUT (1 0) 1 1 0

1 1 0

1 0 1

(1 0) 1

1 1 0 (Binary equivalent: COUT 10)

6.6 • Binary Adders and Subtractors

243

d. COUT (1 1) 0 1 1

0 0 1

0 1 1

(1 1) 0

0 0 0

(Binary equivalent: COUT 10)

In each case, the binary equivalent is the same as the number of HIGH inputs, regard-

less of which inputs they are.

EXAMPLE 6.19

Combine a half adder and a full adder to make a circuit that will add two 2-bit numbers.

Check that the circuit will work by adding the following numbers and writing the binary

equivalents of the inputs and outputs:

a. A2 A1 01, B2 B1 01 b. A2 A1 11, B2 B1 10

SOLUTION The 2-bit adder is shown in Figure 6.9. The half adder combines A1 and B1; A2, B2, and C1 are added in the full adder. The carry output, C1, of the half adder is connected to the carry input of the full adder. (A half adder can be used only in the LSB of a multiple-bit addition.)

FIGURE 6.9

Example 6.19

2-Bit Adder

Sums:

a. 01

01 010

A1 1, B1 1

C1 1, 1 0

A2 0, B2 0, C1 1

C2 0, 2 1

(Binary equivalent: A2 A1 B2 B1 C2 2 1 010)

b. 11 10 101

A1 1, B1 0

C1 0, 1 1

A2 1, B2 1, C1 0

C2 1, 2 0

(Binary equivalent: A2 A1

B2 B1 C2 2 1

101)

244

C H A P T E R 6 • Digital Arithmetic and Arithmetic Circuits

www.electronictech.com

FIGURE 6.10

4-Bit Parallel Binary Adder

Parallel Binary Adder/Subtractor

K E Y T E R M S

Parallel binary adder A circuit, consisting of n full adders, that will add two n-bit binary numbers. The output consists of n sum bits and a carry bit.

Ripple carry A method of passing carry bits from one stage of a parallel adder to

the next by connecting COUT of one full adder to CIN of the following stage.

Cascade To connect an output of one device to an input of another, often for the purpose of expanding the number of bits available for a particular function.

As Example 6.19 implies, a binary adder can be expanded to any number of bits by using a full adder for each bit addition and connecting their carry inputs and outputs in cascade. Figure 6.10 shows four full adders connected as a 4-bit parallel binary adder.

The first stage (LSB) can be either a full adder with its carry input forced to logic 0 or

a half adder, since there is no previous stage to provide a carry. The addition is done one bit

at a time, with the carry from each adder propagating to the next stage.

EXAMPLE 6.20

Verify the summing operation of the circuit in Figure 6.10 by calculating the output for the

following sets of inputs:

a. A4 A3 A2 A1 0101, B4 B3 B2 B1 1001

b. A4 A3 A2 A1 1111, B4 B3 B2 B1 0001

SOLUTION At each stage, A B CIN COUT .

a. 0101 1001 1110

(510 910 1410)

A1 1, B1 1, C0 0; C1 1,

1 0

A2 0, B2 0, C1 1; C2 0,

2 1

A3 1, B3 0, C2 0; C3 0,

3 1

A4 0, B4 1, C3 0;

C4 0, 4 1

(Binary equivalent: C4 4 3 2 1 01110)

6.6 • Binary Adders and Subtractors

245

b.1111 0001 10000

(1510 110 1610)

A1 1, B1 1, C0 0; C1 1, 1 0 A2 1, B2 0, C1 1; C2 1, 2 0 A3 1, B3 0, C2 1; C3 1, 3 0 A4 1, B4 0, C3 1; C4 1, 4 0

(Binary equivalent: C4 4 3 2 1 10000)

The internal carries in the parallel binary adder in Figure 6.10 are achieved by a system called ripple carry. The carry output of one full adder cascades directly to the carry input of the next. Every time a carry bit changes, it “ripples” through some or all of the following stages. A sum is not complete until the carry from another stage has arrived. The equivalent circuit of a 4-bit ripple carry is shown in Figure 6.11.

A4 B4

A

B4

A3B3

4

A3 B3

A2B2

C4

A2 B2

A1B1

A1 B1

C3

C2

C0

C1

FIGURE 6.11

4-bit Ripple Carry Chain

A potential problem with this design is that the adder circuitry does not switch instantaneously. A carry propagating through a ripple adder adds delays to the summation time and, more importantly, can introduce unwanted intermediate states.

Examine the sum (1111 0001 10000). For a parallel adder having a ripple carry, the output goes through the following series of changes as the carry bit propagates through the circuit:

C4 4 3 2 1 01111

01110

01100

01000

10000

If the output of the full adder is being used to drive another circuit, these unwanted intermediate states may cause erroneous operation of the load circuit.

Fast Carry

K E Y T E R M

Fast carry (or look-ahead carry) A gate network that generates a carry bit directly from all incoming operand bits, independent of the operation of each full adder stage.

An alternative carry circuit is called fast carry or look-ahead carry. The idea behind fast carry is that the circuit will examine all the A and B bits simultaneously and produce an output carry that uses fewer levels of gating than a ripple carry circuit. Also, since there is

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