Файл: Digital design with CPLD applications and VHDL (R. Dueck, 2000).pdf

FIGURE 6.12

4-bit Fast Carry Circuit

a carry bit gate network for each internal stage, the propagation delay is the same for each full adder, regardless of the input operands.

The algebraic relation between operand bits and fast carry output is presented below, without proof. It can be developed from the fast carry circuit of Figure 6.12 by tracing the logic of the gates in the circuit.

C4 A4 B4 A3 B3 (A4 B4) A2 B2 (A4 B4)(A3 B3)

A1 B1 (A4 B4)(A3 B3)(A2 B2)

C0 (A4 B4)(A3 B3)(A2 B2)(A1 B1)

We can make some intuitive sense of the above expression by examining it a term at a time. The first term says if the MSBs of both operands are 1, there will be a carry (e.g., 1000 1000 10000; carry generated).

The second term says if both second bits are 1 AND at least one MSB is 1, there will be a carry (e.g., 0100 1100 10000, or 1100 1100 11000; carry generated in either case). This pattern can be followed logically through all the terms.

The internal carry bits are generated by similar circuits that drive the carry input of each full adder stage in the parallel adder. In general, we can generate each internal carry by expanding the following expression:

Cn AnBn Cn 1 (An Bn)

The algebraic expressions for the remaining carry bits are:

C1 A1B1 C0 (A1 B1)

C2 A2B2 A1 B1 (A2 B2) C0 (A2 B2)(A1 B1)

C3 A3B3 A2 B2 (A3 B3) A1 B1 (A3 B3)(A2 B2)C0 (A3 B3)(A2 B2)(A1 B1)

SECTION 6.6A REVIEW PROBLEM

6.9Refer to the logic diagrams for the ripple carry and fast carry circuits (Figures 6.11 and 6.12). How many gates must a carry bit propagate through in each device if the effect of the carry input ripples through to the 4 bit? (See Figure 6.32 on page 273 and Figure 6.33 on page 273.)

Using VHDL Components to Implement a Parallel Adder

K E Y T E R M S

Hierarchy A group of design entities associated in a series of levels or layers in which complete designs form portions of another, more general design entity. The more general design is considered to be the higher level of the hierarchy.

Component A complete VHDL design entity that can be used as a part of a higher-level file in a hierarchical design.

Port An input or output of a VHDL design entity or component.

Component declaration statement A statement that defines the input and output port names of a component used in a VHDL design entity.

Instantiate To use an instance of a component.

Component instantiation statement A statement that maps port names of a VHDL component to the port names, internal signals, or variables of a higher-level VHDL design entity.

VHDL designs can be created using a hierarchy of design entities. Certain functions, such as full adders, decoders, and so on, can be created once and used in many designs or multiple times in a single design.

We can create a parallel adder in VHDL by using multiple instances of a full adder component in the top-level file of a VHDL design hierarchy. Figure 6.13 shows a graphical illustration of this concept. Each full adder shown is an instance of a component written in VHDL, as shown in the following.

Full_add.vhd

We can create the same design as in Figure 6.13 using VHDL only. To make this hierarchical design we require:

1.A separate component file for a full adder (full_add.vhd), saved in a folder where the compiler can find it (i.e., on a library path)

2.A component declaration statement in the top-level file of the design hierarchy

3.A component instantiation statement for each instance of the full adder component

The general form of a design entity using components is:

ENTITY entity_name IS

PORT ( input and output definitions);

END entity_name;

ARCHITECTURE arch_name OF entity_name IS component declaration(s);

signal declaration(s);