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250	C H A P T E R 6 • Digital Arithmetic and Arithmetic Circuits

The component declaration statement deﬁnes the ports of the component with the same names as in the full_add.vhd. Note that the form of the component declaration statement is almost the same as that of the component’s entity declaration. In effect, we are redeﬁning the component entity in the top-level ﬁle of the design hierarchy.

The component instantiation statement is of the following form:

__instance_name: __component_name

GENERIC MAP (__parameter_name __parameter_value , __parameter_name __parameter_value)

PORT MAP (__component_port __connect_port, __component_port __connect_port);

In the generic map, a generalized parameter name can be mapped to a speciﬁc value when the component is instantiated. For example, a parameter name can be given a value that speciﬁes the number of component output bits. We will not use this feature in our present examples.

In the port map, component ports are the names of the ports used in the component ﬁle and connect ports are the names of the ports, variables, or signals used in the higher-level design entity. For example, the component ports of the full adder component are a, b, c in, c_out, and sum. The connect ports for the instance adder1 are a(1), b(1), c0, c(1), and sum(1). The ripple carry from adder1 to adder2 is achieved by mapping the port c_in of adder2 to c(1), which is also mapped to the port c_out of adder1.

We can write the component instantiation statements more efﬁciently if we decide to use all ports of the component in the order they are deﬁned. In this case, we can simply list the connect ports in the port map in the correct order, as follows:

adder1: full_add PORT MAP (a(1),b(1),c0, c(1),sum(1)); adder2: full_add PORT MAP (a(2),b(2),c(1),c(2),sum(2)); adder3: full_add PORT MAP (a(3),b(3),c(2),c(3),sum(3)); adder4: full_add PORT MAP (a(4),b(4),c(3),c4, sum(4));

If we only wish to use some of the component ports or use them in a different order than the order in which theywere originally deﬁned, we must use the previous form of port map (i.e., a a(1), etc.).

GENERATE Statements

K E Y T E R M

GENERATE statement A VHDL construct that is used to create repetitive por-

tions of hardware.

The four component instantiation statements shown previously can be written in a more general form:

adder(i): full_add PORT MAP (a(i), b(i), c(i-1), c(i), sum(i));

A statement that can be written in this indexed form can be implemented using a

GENERATE statement, which has the form:

label:

FOR index IN range GENERATE

statements;

END GENERATE;

The VHDL code that follows shows how to use the statement to create a 4-bit adder.

generate statement

add4gen.vhd

		6.6 • Binary Adders and Subtractors	251
ENTITY add4gen IS
PORT (
c0	: IN	BIT;
a, b	: IN	BIT_VECTOR (4 downto 1);
c4	: OUT	BIT;
sum	: OUT	BIT_VECTOR (4 downto 1));
END add4gen;

ARCHITECTURE adder OF add4gen IS

——Component declaration COMPONENT full_add

PORT (

a, b, c_in : IN BIT; c_out, sum : OUT BIT);

END COMPONENT;

—— Deﬁne a signal for internal carry bits SIGNAL c : BIT_VECTOR (4 downto 0);

BEGIN

c(0) c0; adders:

FOR i IN 1 to 4 GENERATE

adder: full_add PORT MAP (a(i),b(i),c(i-1),c(i),sum(i)); END GENERATE;

c4 c(4); END adder;

The GENERATE statement will create hardware that corresponds to the range of the index variable, i. In this case i goes from 1 to 4, so the statement instantiates four instances of the full adder. Since we have an input carry, an output carry and three internal carries, we must use a 5-bit signal (BIT_VECTOR (4 downto 0)) if we are to include all carry bits in indexed form. The input carry, c0, deﬁned in the entity declaration, is assigned to the vector element c(0). Similarly, the output, c4, is assigned the value of the element c(4).

It is easy to expand the adder width by changing the range of the FOR GENERATE statement. For example, to make an 8-bit adder, we change the vectors to have a width of eight bits. The required VHDL code, shown next, requires the same number of lines of code as the 4-bit adder.

add8gen.vhd			generate statement
			generate statement

ENTITY add8gen IS
PORT (
C0	: IN	BIT;
a, b	: IN	BIT_VECTOR (8 downto 1);
c8	: OUT	BIT;
sum	: OUT	BIT_VECTOR (8 downto 1));
END add8gen;
ARCHITECTURE adder OF add8gen IS
—— Component declaration
COMPONENT full_add
PORT (
	a, b, c_in : IN		BIT;
	c_out, sum : OUT		BIT);

252	C H A P T E R 6 • Digital Arithmetic and Arithmetic Circuits
	END COMPONENT;
	—— Deﬁne a signal for internal carry bits
	SIGNAL c : BIT_VECTOR (8 downto 0);
	BEGIN
	c(0)	c0;
	adders:
	FOR i IN 1 to 8 GENERATE
	adder: full_add PORT MAP (a(i), b(i), c(i-1), c(i),
	sum(i));
	END GENERATE;
	c8	c(8);
	END adder;
	2’s Complement Subtractor
	Recall the technique for subtracting binary numbers in 2’s complement notation. For ex-
	ample, to ﬁnd the difference 0101 0011 by 2’s complement subtraction:
	1. Find the 2’s complement of 0011:
		0011
		1100	(1’s complement)
		1
		1101	(2’s complement)

2. Add the 2’s complement of the subtrahend to the minuend:

0101	( 5)
1101	( 3)
1 0010	( 2)

(Discard carry)

We can easily build a circuit to perform 2’s complement subtraction, using a parallel binary adder and an inverter for each bit of one of the operands. The circuit shown in Figure 6.14 performs the operation (A B).

FIGURE 6.14

2’s Complement Subtractor

The four inverters generate the 1’s complement of B. The parallel adder generates the 2’s complement by adding the carry bit (held at logic 1) to the 1’s complement at the B inputs. Algebraically, this is expressed as:

A B A ( B) A B 1

where B is the 1’s complement of B, and (B 1) is the 2’s complement of B.

			6.6 • Binary Adders and Subtractors	253

EXAMPLE 6.21	Verify the operation of the 2’s complement subtractor in Figure 6.14 by subtracting:
	a.	1001 0011	(unsigned)
	b.	0100 0111	(signed)

SOLUTION Let B be the 1’s complement of B.

a. Inverter inputs (B):	0011
Inverter outputs (B):	1100
Sum (A B 1):	1001	( 9)
	1100	( 3)
	1

1 0110	( 6)
(Discard carry)
(Discard carry)
b. Inverter inputs (B):	0111
Inverter outputs (B):	1000
Sum (A B 1):	0100	( 4)
	1000	( 7)
	1		←
Negative result:	1101	( 3)
Negative result:	1101	( 3)
1’s complement of 1101:	0010
	1
2’s complement of 1101:	0011	( 3)
2’s complement of 1101:	0011	( 3)

Parallel Binary Adder/Subtractor

Figure 6.15 shows a parallel binary adder conﬁgured as a programmable adder/subtractor. The Exclusive OR gates work as programmable inverters to pass B to the parallel adder in either true or complement form, as shown in Figure 6.16.

FIGURE 6.15

2’s Complement Adder/Subtractor

254	C H A P T E R 6 • Digital Arithmetic and Arithmetic Circuits

FIGURE 6.16

XOR as a Programmable Inverter

The ADD/SUB input is tied to the XOR inverter/buffers and to the carry input of the parallel adder. When ADD/SUB 1, B is complemented and the 1 from the carry input is added to the complement sum. The effect is to subtract (A B). When ADD/SUB 0, the B inputs are presented to the adder in true form and the carry input is 0. This produces an output equivalent to (A B).

This circuit can add or subtract 4-bit signed or unsigned binary numbers.

6.22Write a VHDL ﬁle to implement the 4-bit adder/subtractor shown in Figure 6.15. Also create a simulation ﬁle to test a representative selection of addition and subtraction operations.

SOLUTION The VHDL ﬁle is as follows:

addsub4g.vhd

sub	: IN	BIT;
a, b	: IN	BIT_VECTOR (4 downto 1);
c4	: OUT	BIT;
sum	: OUT	BIT_VECTOR (4 downto 1));
END addsub4g;
ARCHITECTURE adder OF addsub4g IS
—— Component declaration
COMPONENT full_add
PORT (
a, b, c_in : IN			BIT;
c_out, sum : OUT			BIT);
END COMPONENT;
—— Deﬁne a signal for internal carry bits
SIGNAL c	: BIT_VECTOR (4 downto 0);