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284 C H A P T E R 7 • Introduction to Sequential Logic

Note that the latch is not stable in its new condition until the new logic levels have propagated through both gates. Figure 7.16 shows the result of a RESET pulse that only lasts for 7.5 ns. This pulse is too short to allow both gates to change states. The outputs both oscillate, since the changing logic levels never “catch up” as they move around the latch. This is due to the fact that both paths (nS-Q-nQ and nR-nQ-Q) are the same length. If one path were slightly longer, the logic level controlled by the longer path would dominate and the latch would stabilize in one state or the other.

FIGURE 7.16

NAND latch oscillation due to a

RESET pulse that is too short

S 0

Q 1

1

1

Q 1

R 0

FIGURE 7.17

NAND Latch Forbidden State

FIGURE 7.18

SET goes HIGH before RESET

FIGURE 7.19

RESET goes HIGH before SET

Figure 7.17 shows a NAND latch with S R 0. This implies that both SET and RESET functions are active. Since a NAND gate requires at least one input LOW to make the output HIGH, both outputs respond by going HIGH. This condition is not unstable in and of itself, but instability can result when the inputs change.

There are three possible results when the outputs go back to the HIGH state.

1.The SET input goes HIGH before the RESET input. In this case the latch resets, as RESET is the last input active. This is shown in the simulation in Figure 7.18.

2.The RESET input goes HIGH before SET. In this case, the latch sets, as shown in Figure 7.19.

7.2 • NAND/NOR Latches

285

3.The SET and RESET inputs go HIGH at the same time. This is an unstable case. Figure 7.20 shows how the latch will oscillate under this condition. When the inputs S and R are both LOW (Figure 7.20a), both latch outputs are HIGH. When S and R go HIGH (Figure 7.20b), all gate inputs are HIGH. This makes both outputs LOW (Figure 7.20c). The LOWs transfer across the latch to the opposite gates and, after a delay, make both outputs HIGH (Figure 7.20d). At this point, oscillations will be sustained until the latch is SET or RESET. The simulation waveforms in Figure 7.21 show the oscillatory condition of the latch outputs.

S 0

Q 1

S 1

Q 1

S 1

Q 0

1

1

0

1

Q 1

1

Q 1

0

Q 0

R 0

R 1

R 1

a. t 0

b. t 0

c. t 7.5ns

S 1

Q 1

S 1

Q 0

1

0

1

Q 1

0

Q 0

R 1

R 1

d. t 12.5ns

e. t 17.5ns

FIGURE 7.20

NAND Latch Forbidden State Transition

In practice, the oscillatory condition of Figure 7.21 is unlikely to be sustained for very long. One of the two gates is likely to be slightly faster than the other, which will allow one state or the other to dominate.

FIGURE 7.21

SET and RESET go HIGH simultaneously

The operation of the NAND latch can be summarized in a function table, shown in Table 7.2. The notation Qt 1 indicates that the column shows the value of Q after the specified input is applied. Qt indicates the present state of the Q input.* Thus, the entry for the no change state indicates that after the inputs S 0, R 0 are applied, the next state of the output is the same as its present state.

*Many sources (such as data sheets) use the notation Q0 to refer to the previous state of Q. We will use the notation indicated (Qt for present state and Qt 1 for next state) so as to be able to reserve Q0 for the least significant bit of a circuit requiring multiple Q outputs.

286 C H A P T E R 7 • Introduction to Sequential Logic

FIGURE 7.22

NAND Latch as synthesized by MAX PLUS II (NORMAL synthesis)

Table 7.2 NAND Latch Function Table

S

R

Qt 1

Qt 1

Function

0

0

1

1

Forbidden

0

1

1

0

Set

1

0

0

1

Reset

1

1

Qt

Qt

No Change

Table 7.3 NOR Latch Function Table

S

R

Qt 1

Qt 1

Function

0

0

Qt

Qt

No Change

0

1

0

1

Reset

1

0

1

0

Set

1

1

0

0

Forbidden

Table 7.3 shows the function table for the NOR latch.

Practical Synthesis in MAX PLUS II

The NAND latch shown previously (Figure 7.8) was synthesized in MAX PLUS II, using the WYSIWYG synthesis style. We did this so as to be able to use the MAX PLUS II simulation tool to get waveforms for a standard NAND latch. However, if we allow MAX PLUS II to synthesize the latch circuit in the Normal synthesis style, the software will choose a more stable configuration, shown in Figure 7.22.

nS

Q

nR

nQ

Vcc

The equations for the circuit in Figure 7.22 from the MAX PLUS II report file are given as:

** EQUATIONS **

nR

:

INPUT;

nS

:

INPUT;

——Node name is ‘nQ’

——Equation name is ‘nQ’, location is LC117, type is output. nQ LCELL( _EQ001 $ VCC);

_EQ001 nR & Q;

——Node name is ´Q´ ´ 2 1´

——Equation name is ´Q´, location is LC115, type is output. Q LCELL( _EQ002 $ !ns);

_EQ002 nR & nS & Q;

We can rewrite the above equations as:

Q (nR nS Q) nS

nQ (nR Q) 1 nR Q

Without going into a detailed analysis, we will just note that the latching occurs through a combination of the XOR gate at Q and the feedback from the Q output to the 3- input AND. The lower AND/XOR structure simply serves to invert the Q output to provide a complementary value at nQ.

This configuration is more stable because both SET and RESET functions go through the same path (the 3-input AND gate). Delay is the same from nS to Q and from nR to Q. In the WYSIWYG version, the path is equal from nS to nQ and from nR to Q, but not from nS to Q and nR to Q. The SET and RESET pulses thus go through different paths in the

7.2 • NAND/NOR Latches

287

WYSIWYG synthesis, resulting in unequal delays from the inputs to the Q output, which can lead to instability.

Latch as a Switch Debouncer

Pushbutton or toggle switches are sometimes used to generate pulses for digital circuit inputs, as illustrated in Figure 7.23. However, when a switch is operated and contact is made on a new terminal, the contact, being mechanical, will bounce a few times before settling into the new position. Figure 7.23d shows the effect of contact bounce on the waveform for a pushbutton switch. The contact bounce is shown only on the terminal where contact is being made, not broken.

FIGURE 7.23

Switches as Pulse Generators

Contact bounce can be a serious problem, particularly when a switch is used as an input to a digital circuit that responds to individual pulses. If the circuit expects to receive one pulse, but gets several from a bouncy switch, it will behave unpredictably.

A latch can be used as a switch debouncer, as shown in Figure 7.24a. When the pushbutton is in the position shown, the latch is set, since S 0 and R 1. (Recall that the NAND latch inputs are active LOW.) When the pushbutton is pressed, the R contact

FIGURE 7.24

NAND Latch as a Switch

Debouncer

288 C H A P T E R 7 • Introduction to Sequential Logic

bounces a few times, as shown in Figure 7.24b. However, on the first bounce, the latch is reset. Any further bounces are ignored, since the resulting input state is either S R 1 (no change) or S 1, R 0 (reset).

Similarly, when the pushbutton is released, the S input bounces a few times, setting the

latch on the first bounce. The latch ignores any further bounces, since they either do not

change the latch output (S R 1) or set it again (S 0, R 1). The resulting waveforms

at Q and Q are free of contact bounce and can be used reliably as inputs to digital sequen-

tial circuits.

EXAMPLE 7.3

A NOR latch can be used as a switch debouncer, but not in the same way as a NAND latch.

Figure 7.25 shows two NOR latch circuits, only one of which works as a switch debouncer.

Draw a timing diagram for each circuit, showing R, S, Q, and Q, to prove that the circuit in

Figure 7.25b eliminates switch contact bounce but the circuit in Figure 7.25a does not.

FIGURE 7.25

Example 7.3

NOR Latch Circuits

SOLUTION Figure 7.26 shows the timing diagrams of the two NOR latch circuits. In the circuit in Figure 7.25a, contact bounce causes the latch to oscillate in and out of the forbidden state of the latch (S R 1). This causes one of the two outputs to bounce for each contact closure. (Use the function table of the NOR latch to examine each part of the timing diagram to see that this is so.)

By making the resistors pull down rather than pull up, as in Figure 7.25b, the latch oscillates in and out of the no change state (S R 0) as a result of contact bounce. The first

FIGURE 7.26

Example 7.3

NOR Latch Circuits

7.3 • Gated Latches

289

bounce on the SET terminal sets the latch, and other oscillations are disregarded. The first bounce on the RESET input resets the latch, and further pulses on this input are ignored.

The principle illustrated here is that a closed switch must present the active input level to the latch, since switch bounce is only a problem on contact closure. Thus, a closed switch must make the input of a NOR latch HIGH or the input of a NAND latch LOW to debounce the switch waveform.

N O T E

The NOR latch is seldom used in practice as a switch debouncer. The pull-down resistors need to be about 500 or less to guarantee a logic LOW at the input of a TTL NOR gate. In such a case, a constant current of about 10 mA flows through the resistor connected to the normally closed portion of the switch. This value is unacceptably high in most circuits, as it draws too much idle current from the power supply. For this reason, the NAND latch, which uses higher-value pull-up resistors (about 1 k or larger) and therefore draws less idle current, is preferred for a switch debouncer.

SECTION 7.2 REVIEW PROBLEM

7.2Why is the input state S R 1 considered forbidden in the NOR latch? Why is the same state in the NAND latch the no change condition?

7.3Gated Latches

K E Y T E R M S

Gated SR latch An SR latch whose ability to change states is controlled by an extra input called the ENABLE input.

Steering gates Logic gates, controlled by the ENABLE input of a gated latch, that

steer a SET or RESET pulse to the correct input of an SR latch circuit.

Transparent latch (gated D latch) A latch whose output follows its data input when its ENABLE input is active.

Gated SR Latch

It is not always desirable to allow a latch to change states at random times. The circuit shown in Figure 7.27, calleda gated SR latch, regulates the times when a latch is allowed to change state.

The gated SR latch has two distinct subcircuits. One pair of gates is connected as an SR latch. A second pair, called the steering gates, can be enabled or inhibited by a control signal, called ENABLE, allowing one or the other of these gates to pass a SET or RESET signal to the latch gates.

The ENABLE input can be used in two principal ways: (1) as an ON/OFF signal, and

(2) as a synchronizing signal.

Figure 7.27b shows the ENABLE input functioning as an ON/OFF signal. When ENABLE 1, the circuit acts as an active-HIGH latch. The upper gate converts a HIGH at S to a LOW at S, setting the latch. The lower gate converts a HIGH at R to a LOW at R, thus resetting the latch.

When ENABLE 0, the steering gates are inhibited and do not allow SET or RESET signals to reach the latch gate inputs. In this condition, the latch outputs cannot change.

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