Файл: Digital design with CPLD applications and VHDL (R. Dueck, 2000).pdf

SECTION 7.1 REVIEW PROBLEM

7.1A latch with active-HIGH S and R inputs is initially set. R is pulsed HIGH three times, with S 0. Describe how the latch responds.

7.2NAND/NOR Latches

An SR latch is easy to build with logic gates. Figure 7.6 shows two such circuits, one made from NOR gates and one from NANDs. The NAND gates in the second circuit are drawn in DeMorgan equivalent form.

FIGURE 7.6

SR Latch Circuits

The two circuits both have the following three features:

1.OR-shaped gates

2.Logic level inversion between the gate input and output

3.Feedback from the output of one gate to an input of the opposite gate

During our examination of the NAND and NOR latches, we will discover why these features are important.

A significant difference between the NAND and NOR latches is the placement of SET and RESET inputs with respect to the Q and Q outputs. Once we define which output is Q and which is Q, the locations of the SET and RESET inputs are automatically defined.

In a NOR latch, the gates have active-HIGH inputs and active-LOW outputs. When the input to the Q gate is HIGH, Q 0, since either input HIGH makes the output LOW. Therefore, this input must be the RESET input. By default, the other is the SET input.

In a NAND latch, the gate inputs are active LOW (in DeMorgan equivalent form) and the outputs are active HIGH. A LOW input on the Q gate makes Q 1. This, therefore, is the SET input, and the other gate input is RESET.

Since the NAND and NOR latch circuits have two binary inputs, there are four possible input states. Table 7.1 summarizes the action of each latch for each input combination. The functions are the same for each circuit, but they are activated by opposite logic levels.

Table 7.1 NOR and NAND Latch Functions

280 C H A P T E R 7 • Introduction to Sequential Logic

We will examine the NAND latch circuit for each of the input conditions in Table 7.1.

The analysis of a NOR latch is similar and will be left as an exercise.

NAND Latch Operation

Figure 7.7 shows a NAND latch in its two possible stable states. In each case the inputs S and R are both HIGH (inactive).

FIGURE 7.7

NAND Latch Stable States

Figure 7.7a shows the latch in its SET condition (Q 1). The feedback connections from each gate output to the input of the opposite gate keep the latch in a stable condition. The upper gate has a LOW on the “inner” input. Since, for a NAND gate, either input LOW makes the output HIGH, this makes Q 1. This HIGH value is fed to the gate on the other side of the latch. The lower gate has both inputs HIGH, thus keeping its output LOW. The LOW at Q feeds back to the upper gate, forming a closed loop of consistent logic levels. There is no tendency for the outputs to change under these conditions.

Figure 7.7b shows a similar state for the latch in a RESET condition (Q 0). As with the SET state, the stability of the latch depends on the feedback connections. The logic values of the latch gate inputs are the same as before, except that the LOW input is on the lower gate, not the upper gate as in the SET condition.

Figure 7.8 shows a NAND latch as a Graphic Design File created with MAX PLUS II. The inputs are labeled nS and nR and one output as nQ as we cannot enter input names with bars over them. (BOR2 “Bubbled OR, 2-inputs”.)

Q

BOR2

OUTPUT

nR

FIGURE 7.8

Graphic Design File representation of a NAND Latch.

N O T E

The documentation for MAX PLUS II recommends that you do not create your own latch circuits or similar cross-coupled structures. Rather, you should use primitives such as LATCH, or components such as lpm_latch, which can be used in gdf or vhd files. We will use the design in Figure 7.8 only to illustrate the function of a NAND latch and to generate some timing data with the MAX PLUS II simulator.

In order to make MAX PLUS II synthesize this circuit as we have drawn it in Figure 7.8, we must select Global Project Logic Synthesis from the Assign Menu (Figure 7.9).

282 C H A P T E R 7 • Introduction to Sequential Logic

When we run the MAX PLUS II Timing Analyzer, we get the delay matrix shown in Figure 7.11. The delays are symmetrical for this circuit. The delay from nS to Q (7.5 ns) is through one gate; from nS to nQ (12.5 ns) is through two gates. These values are the same for the path from nR to nQ (7.5 ns; one gate) and from nR to Q (12.5 ns; two gates). We can see these changes on simulation waveforms for the SET and RESET functions.

FIGURE 7.12

RESET-to-SET transition

FIGURE 7.13

NAND Latch SET function simulation

The waveforms in Figure 7.13 also show this transition. The simulation window has a 2.5 ns grid, so three grid spaces are equivalent to 7.5 ns and five grid spaces to 12.5 ns. The waveforms show Q going HIGH 7.5 ns after nS goes LOW, followed by nQ going LOW at 12.5 ns after nS.

Figures 7.14 and 7.15 show the same thing for the RESET function. The latch is in a stable SET condition at time t 0 (Figure 7.14a). Input R goes LOW at t 0 (Figure 7.14b). At time t 7.5 ns, Q goes HIGH, which is transferred to the upper gate in the latch circuit Figure 7.14c). Since both inputs of the upper gate are now HIGH, Q goes LOW at time t 12.5 ns (Figure 7.14d). At this point the latch is stable in the RESET condition and the input R can return to the HIGH (inactive) state, as shown in Figure 7.14e. Figure 7.15 shows the simulation waveforms for this transition.

FIGURE 7.14

SET-to-RESET Transition

FIGURE 7.15

NAND latch RESET function simulation