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272

C H A P T E R 6 • Digital Arithmetic and Arithemtic Circuits

6.32Create a simulation for the 4-bit adder/subtractor with overflow detection (Problem 6.31), using the following representative hexadecimal input values: F 1 10 (carry, but no overflow); 7 1 8 (overflow, but no carry); 8 8 10 (carry and overflow); 0 1 F (result 1).

6.33Modify the VHDL file for the 4-bit parallel binary adder/subtractor (addsub4g.vhd) to include an overflow detection circuit. Use two different methods.

6.34What is the permissible range of values that a sum or difference, x, can have in a 16-bit parallel binary adder if it is written as:

a.A signed binary number

b.An unsigned binary number

Section 6.7 BCD Adders

6.35What is the maximum BCD sum of two 3-digit BCD numbers plus an input carry? How many digits are needed to display the result?

6.36What is the maximum BCD sum of two 4-digit BCD numbers plus an input carry? How many digits are needed to display the result?

6.37Based on the answers to Problems 6.35 and 6.36, formulate a general rule to calculate the maximum BCD sum of two n-digit BCD numbers plus a carry bit.

6.38Derive the Boolean expression for a BCD carry output as a function of the sum of two BCD digits.

6.39Draw the circuit for a binary-to-BCD code converter.

6.40Write a VHDL file to implement a binary-to-BCD code converter for a BCD adder. Use a selected signal assignment or CASE statement.

6.41Write a VHDL file that uses the binary-to-BCD code converter of Problem 6.40 and a 4-bit parallel binary adder as components in a BCD adder.

6.42Write a VHDL file that uses a code converter and parallel adder as components in a design that will add two 2-digit BCD numbers and produce a 21⁄2 digit result.

6.43Draw the block diagram of a circuit that will add two 3-digit BCD numbers and display the result as a series of decimal digits. How many digits will the output display?

A N S W E R S T O S E C T I O N R E V I E W P R O B L E M S

Section 6.1a

6.1

101000;

6.2

100000.

Section 6.1b

6.3

11;

6.4

1

Section 6.3

6.5

11100000;

6.6

100000.

Section 6.4

6.7a

11701H

6.7b

1281H

Section 6.5

6.8 “True or False: 1/4 1/2”

Section 6.6a

6.9 Figures 6.32 and 6.33 show the propagation paths for the carry bits.

Fast carry: 3 gates

Ripple carry: 8 gates

Section 6.6b

6.10a Signed: 2048 x 2047 (11 magnitude bits, 1 sign bit)

6.10b Unsigned: 0 x 4095 (12 magnitude bits, no sign bit: positive implied)

Section 6.7

6.11 Maximum BCD sum 1001 1001 1001 1001 1001 1001 1 1001 1001 1000BCD 199810. This sum requires a 312 -digit numerical display.


Answers to Section Review Problems

273

a1

INPUT

AND2

INPUT

b1

OR2

a2

INPUT

AND2

INPUT

b2

OR2

a3

INPUT

AND2

INPUT

b3

OR2

a4

INPUT

AND2

INPUT

b4

OR2

c0

INPUT

OR2

AND2

c1

OUTPUT

c1

OR3

AND2

c2

OUTPUT

c2

AND3

OR4

AND2

c3

OUTPUT

c3

AND3

AND4

OR6

AND2

c4

OUTPUT

c4

AND3

AND4

GND

AND6

VCC

FIGURE 6.32

Fast Carry from A4/B4 to C4.

A4B4

A4 B4

A3B3

A2B2

A3 B3

C4

A2 B2

A1B1

A1 B1

C0

FIGURE 6.33

Ripple Carry from C0 to C4


C H A P T E R 7

Introduction to Sequential Logic

O U T L I N E

C H A P T E R O B J E C T I V E S

7.1 Latches

Upon successful completion of this chapter, you will be able to:

7.2NAND/NOR Latches • Explain the difference between combinational and sequential circuits.

7.3 Gated Latches

• Define the set and reset functions of an SR latch.

7.4Edge-Triggered D • Draw circuits, function tables, and timing diagrams of NAND and NOR

Flip-Flops

latches.

7.5Edge-Triggered JK • Explain the effect of each possible input combination to a NAND and a

Flip-Flops

NOR latch, including set, reset, and no change functions, as well as the am-

7.6

Edge-Triggered T

biguous or forbidden input condition.

Flip-Flops

Design circuit applications that employ NAND and NOR latches.

7.7

Timing Parameters

Describe the use of the ENABLE input of a gated SR or D latch as an en-

able/inhibit function and as a synchronizing function.

Outline the problems involved with using a level-sensitive ENABLE input

on a gated SR or D latch.

Explain the concept of edge-triggering and why it is an improvement over

level-sensitive enabling.

Draw circuits, function tables, and timing diagrams of edge-triggered D,

JK, and T flip-flops.

Describe the toggle function of a JK flip-flop and a T flip-flop.

Describe the operation of the asynchronous preset and clear functions of D,

JK, and T flip-flops and be able to draw timing diagrams showing their

functions.

• Use MAX PLUS II to create simple circuits and simulations with D latches and D, JK, and T flip-flops.

• Create simple flip-flop designs using VHDL.

The digital circuits studied to this point have all been combinational circuits, that is, circuits whose outputs are functions only of their present inputs. A particular set of input

states will always produce the same output state in a combinational circuit.

275


276 C H A P T E R 7 • Introduction to Sequential Logic

This chapter will introduce a new category of digital circuitry: the sequential circuit. The output of a sequential circuit is a function both of the present input conditions and the previous conditions of the inputs and/or outputs. The output depends on the sequence in which the inputs are applied.

We will begin our study of sequential circuits by examining the two most basic sequential circuit elements: the latch and the flip-flop, both of which are part of the general class of circuits called bistable multivibrators. These are similar devices, each being used to store a single bit of information indefinitely. The difference between a latch and a flipflop is the condition under which the stored bit is allowed to change.

Latches and flip-flops are also used as integral parts of more complex devices, such as programmable logic devices (PLDs), usually when an input or output state must be stored.

7.1 Latches

K E Y T E R M S

Sequential circuit A digital circuit whose output depends not only on the present combination of inputs, but also on the history of the circuit.

Latch A sequential circuit with two inputs called SET and RESET, which make the latch store a logic 0 (reset) or 1 (set) until actively changed.

SET 1. The stored HIGH state of a latch circuit.

2. A latch input that makes the latch store a logic 1.

RESET 1. The stored LOW state of a latch circuit.

2. A latch input that makes the latch store a logic 0.

All the circuits we have seen up to this point have been combinational circuits. That is, their present outputs depend only on their present inputs. The output state of a combinational circuit results only from a combination of input logic states.

The other major class of digital circuits isthe sequential circuit. The present outputs of a sequential circuit depend not only on its present inputs, but also on its past input states.

The simplest sequential circuit is the SR latch, whose logic symbol is shown in Figure 7.1a. The latch has two inputs, SET (S) and RESET (R), and two complementary outputs, Q and Q. If the latch is operating normally, the outputs are always in opposite logic states.

FIGURE 7.1

SR Latch (Active HIGH Inputs)

The latch operates like a momentary-contact pushbutton with START and STOP functions, shown in Figure 7.2. A momentary-contact switch operates only when it is held down. When released, a spring returns the switch to its rest position.

Suppose the switch in Figure 7.2 is used to control a motor starter. When you push the START button, the motor begins to run. Releasing the START switch does not turn the motor off; that can be done only by pressing the STOP button. If the motor is running,


7.1 • Latches

277

FIGURE 7.2

Industrial Pushbutton (e.g.,

Motor Starter)

pressing the START button again has no effect, except continuing to let the motor run. If the motor is not running, pressing the STOP switch has no effect, since the motor is already stopped.

There is a conflict if we press both switches simultaneously. In such a case we are trying to start and stop the motor at the same time. We will come back to this point later.

The latch SET input is like the START button in Figure 7.2. The RESET input is like the STOP button.

N O T E

By definition:

A latch is set when Q 1 and Q 0.

A latch is reset when Q 0 and Q 1.

The latch in Figure 7.1 has active-HIGH SET and RESET inputs. To set the latch, make R 0 and make S 1. This makes Q 1 until the latch is actively reset, as shown in the timing diagram in Figure 7.1b. To activate the reset function, make S 0 and make R 1. The latch is now reset (Q 0) until the set function is next activated.

Combinational circuits produce an output by combining inputs. In sequential circuits, it is more accurate to think in terms of activating functions. In the latch described, S and R are not combined by a Boolean function to produce a particular result at the output. Rather, the set function is activated by making S 1, and the reset function is activated by making R 1, much as we would activate the START or STOP function of a motor starter by pressing the appropriate pushbutton.

The timing diagram in Figure 7.1b shows that the inputs need not remain active after the set or reset functions have been selected. In fact, the S or R input must be inactive before the opposite function can be applied, in order to avoid conflict between the two functions.

EXAMPLE 7.1

Latches can have active-HIGH or active-LOW inputs, but in each case Q 1 after the set

function is applied and Q 0 after reset. For each latch shown in Figure 7.3, complete the

timing diagram shown. Q is initially LOW in both cases. (The state of Q before the first ac-

tive SET or RESET is unknown unless specified, since the present state depends on previ-

ous history of the circuit.)

FIGURE 7.3

Example 7.1

SR Latch