Файл: Digital design with CPLD applications and VHDL (R. Dueck, 2000).pdf

Steering gates Logic gates, controlled by the ENABLE input of a gated latch, that steer a SET or RESET pulse to the correct input of an SR latch circuit.

Synchronous Synchronized to the system clock.

Synchronous inputs The inputs of a flip-flop that do not affect the flip-flop’s Q outputs unless a clock pulse is applied. Examples include D, J, and K inputs.

Problems 317

Toggle Alternate between binary states with each applied clock pulse.

T (toggle) flip-flop A flip-flop whose output toggles between HIGH and LOW states on each applied clock pulse when a synchronous input, called T, is active.

Transparent latch (gated D latch) A latch whose output follows its data input when its ENABLE input is active.

Section 7.1 Latches

7.1Complete the timing diagram in Figure 7.66 for the ac- tive-HIGH latch shown. The latch is initially set.

7.2Repeat Problem 7.1 for the timing diagram shown in Figure 7.67.

FIGURE 7.66

Problem 7.1

Timing Diagram

7.3Complete the timing diagram in Figure 7.68 for the ac- tive-LOW latch shown.

7.4Figure 7.69 shows an active-LOW latch used to control a motor starter. The motor runs when Q 1 and stops when Q 0. (Problem continues . . .)

The motor is housed in a safety enclosure that has an access hatch for service. A safety interlock prevents the motor from running when the hatch is open. The HATCH switch opens when the hatch opens, supplying a logic HIGH to the circuit. The START switch is a normally open momentary-contact pushbutton (LOW when pressed). The STOP switch is a normally closed momen- tary-contact pushbutton (HIGH when pressed).

Draw the timing diagram of the circuit, showing START, STOP, HATCH, S, R, and Q for the following sequence of events:

a.START is pressed and released.

b.The hatch cover is opened.

c.START is pressed and released.

d.The hatch cover is closed.

e.START is pressed and released.

f.STOP is pressed and released.

Briefly describe the functions of the three switches and how they affect the motor operation.

Section 7.2 NAND/NOR Latches

7.5Draw a NAND latch, correctly labeling the inputs and

outputs. Describe the operation of a NAND latch for all four possible combinations of S and R.

7.6Draw a NOR latch, correctly labeling the inputs and outputs. Describe the operation of a NOR latch for all four possible combinations of S and R.

7.7The timing diagram in Figure 7.70 shows the input waveforms of a NAND latch. Complete the diagram by showing the output waveforms.

FIGURE 7.70

Problem 7.7

Timing Diagram

FIGURE 7.71

Problem 7.8

Input Waveforms to a NOR

Latch

FIGURE 7.72

Problem 7.9

Input Waveforms to a Latch

7.8Figure 7.71 shows the input waveforms to a NOR latch. Draw the corresponding output waveforms.

7.9Figure 7.72 represents two input waveforms to a latch circuit.

a.Draw the outputs Q and Q if the latch is a NAND latch.

b.Draw the output waveforms if the latch is a NOR latch.

(Note that in each case, the waveforms will produce the forbidden state at some point. Even under this condition, it is still possible to produce unambiguous output waveforms. Refer to Figures 7.18 and 7.19 for guidance.)

7.10a. Draw a timing diagram for a NAND latch showing each of the following sequences of events:

i.S and R are both LOW; S goes HIGH before R.

ii.S and R are both LOW; R goes HIGH before S.

iii.S and R are both LOW; S and R go HIGH simultaneously.

b.State why S R 0 is a forbidden state for the NAND latch.

c.Briefly explain what the final result is for each of the above transitions.

7.11a Draw a timing diagram for a NOR latch showing each of the following sequences of events:

i.S and R are both HIGH; S goes LOW before R.

ii.S and R are both HIGH, R goes LOW before S.

iii.S and R are both HIGH, S and R go LOW simultaneously.

b.Briefly explain what the final result is for each of the transitions listed in part a of this question.

c.State why S R 1 is a forbidden state for the NOR latch.

7.12Figure 7.73 shows the effect of mechanical bounce on the switching waveforms of a single-pole double-throw (SPDT) switch.

a.Briefly explain how this effect arises.

FIGURE 7.73

Problem 7.12

Effect of Mechanical Bounce on a SPDT Switch

FIGURE

Problem

Gated

FIGURE 7.75

Problem 7.14

Gated Latch

Problems 319

b.Draw a NAND latch circuit that can be used to eliminate this mechanical bounce, and briefly explain how it does so.

Section 7.3 Gated Latches

7.13Complete the timing diagram for the gated latch shown in Figure 7.74.

7.14Complete the timing diagram for the gated latch shown in Figure 7.75.

7.15A pump motor can be started at two different locations

with momentary-contact pushbuttons S1 and S2. It can be stopped by momentary-contact pushbuttons ST1 and ST2. As in Problem 7.4, a RUN input on the motor controller must be kept HIGH to keep the motor running. After the motor is stopped, a timer prevents the motor from starting for 5 minutes.

Draw a circuit block diagram showing how an SR latch and some additional gating logic can be used in

FIGURE 7.76

Problem 7.16

Waveforms

FIGURE 7.77

Problem 7.17

Waveforms

such an application. The timer can be shown as a block activated by the STOP function. Assume that the timer output goes HIGH for 5 minutes when activated.

7.16The S and R waveforms in Figure 7.76 are applied to two different gated latches. The ENABLE waveforms for the

latches are shown as EN1 and EN2. Draw the output waveforms Q1 and Q2, assuming that S, R, and EN are all active HIGH. Which output is least prone to synchronization errors? Why?

7.17Figure 7.77 represents the waveforms of the EN and D inputs of a 4-bit transparent latch. Complete the timing diagram by drawing the waveforms for Q1 to Q4.

7.18An electronic direction finder aboard an aircraft uses a 4- bit number to distinguish 16 different compass points as follows:

Problems 321

The output of the direction finder is stored in a 4-bit latch so that the aircraft flight path can be logged by a computer. The latch is periodically updated by a continuous pulse on the latch enable line.

Figure 7.78 shows a sample reading of the direction finder’s output as presented to the latch. (Problem continues . . .)

N

S

NNE

N

E

ES

a.Complete the timing diagram by filling in the data for the Q outputs.

b.Based on the completed timing diagram of Figure 7.78, make a rough sketch of the aircraft’s flight path for the monitored time.

7.19Write a VHDL file for an 8-bit latch, using LATCH primitives. Create a simulation file that demonstrates the operation of all eight bits.

7.20Write a VHDL file for an 8-bit latch, using a component from the Library of Parameterized Modules. Create a simulation file that tests the latch for all eight bits.

Section 7.4 Edge-Triggered D Flip-Flops

7.21The waveforms in Figure 7.79 are applied to the inputs of a positive edge-triggered D flip-flop and a gated D latch.

Complete the timing diagram where Q1 is the output of the flip-flop and Q2 is the output of the gated latch. Ac-

FIGURE 7.79

Problem 7.21

Waveforms

FIGURE 7.80

Problem 7.22

Waveforms

FIGURE 7.81

Problem 7.23

Waveforms

count for any differences between the Q1 and Q2 waveforms.

7.22Complete the timing diagram for a positive edge-trig- gered D flip-flop if the waveforms shown in Figure 7.80 are applied to the flip-flop inputs.

7.23Repeat Problem 7.22 for the waveforms shown in Figure 7.81.

7.24Repeat Problem 7.22 for the waveforms shown in Figure 7.82.

7.25Draw a logic diagram of a D flip-flop configured for toggle mode. (Hint: The D input must always be the opposite of the Q output.)

7.26Write a VHDL file that defines a 12-bit D flip-flop with a clock common to all flip-flops, using MAX PLUS II primitives. The component declaration for the DFF component is as follows: