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410C H A P T E R

pre_lpm8.vhd

9 • Counters and Shift Registers

ENTITY pre_lpm8 IS

PORT (

clk, count_ena

: IN

STD_LOGIC;

clear, load, direction

: IN

STD_LOGIC;

p

: IN

STD_LOGIC_VECTOR(7 downto 0);

qd

: OUT

STD_LOGIC_VECTOR(7 downto 0));

END pre_lpm8;

ARCHITECTURE a OF pre_lpm8 IS

BEGIN

counter1: lpm_counter

GENERIC MAP (LPM_WIDTH => 8)

PORT MAP ( clock

=> clk,

updown

=> direction,

cnt_en

=> count_ena,

data

=> p,

aload

=> load,

aclr

=> clear,

q

=> qd);

END a;

9.9

Write a VHDL file that uses an LPM counter to generate a DOWN counter with a modulus

of 500. Create a MAX PLUS II simulation file to verify the counter’s operation.

Solution A mod-500 counter requires nine bits since 28 500 29. Since the counter always counts DOWN, we can use the parameter LPM_DIRECTION to specify the DOWN counter rather than using an unnecessary port. The required VHDL code is given below.

Note that the value of LPM_WIDTH is written without quotes, since it is defined as type POSITIVE in the component declaration. LPM_MODULUS and LPM_DIRECTION are written in double quotes, since the component declaration defines them as type STRING.

_lpm.vhd _lpm.scf

Use lpm.lpm_components.ALL;

ENTITY mod5c_lpm IS

PORT (

clk

: IN

STD_LOGIC;

q

: OUT

STD_LOGIC_VECTOR (8 downto 0) );

END mod5c_lpm;

ARCHITECTURE a OF mod5c_lpm IS

BEGIN

counter1: lpm_counter

GENERIC MAP(LPM_WIDTH => 9,

LPM_DIRECTION => “DOWN”,

LPM_MODULUS => “500”)

PORT MAP ( clock => clk, q => q);

END a;

Figure 9.53 shows a partial simulation of the counter, indicating the point at which the output rolls over from 0 to 499 (decimal).

9.6 • Programming Presettable and Bidirectional Counters in VHDL

411

FIGURE 9.53

Example 9.9

Partial Simulation of a Mod-500 LPM DOWN Counter

If we are designing a counter for the Altera UP-1 circuit board, we can simulate the on-board oscillator by choosing a clock period of 40 ns, which corresponds to a clock frequency of 25 MHz. The default simulation period is from 0 to 1 s, which only gives 1 s40 ns/clock period 25 clock periods. This is not enough time to show the entire count cycle. The minimum value for the end of the simulation time is:

40 ns/clock period 500 clock periods 20000 ns 20 s.

If we wish to see a few clock cycles past the recycle point, we can set the simulation end time to 20.1 s. (In the MAX PLUS II Simulator window, select File menu; End Time. Enter the value 20.1us (no spaces) into the Time window and click OK.)

To view the count waveform, q, in decimal rather than hexadecimal, select the waveform by clicking on it. Either right-click to get a pop-up menu or select Enter Group from the simulator Node menu, as in Figure 9.54. This will bring up the Enter Group dialog box shown in Figure 9.55. Select DEC (for decimal) and click OK.

FIGURE 9.54

Selecting a Group in a MAX PLUS II Simulation

FIGURE 9.55

Changing the Name or Radix of a Group

412

C H A P T E R

9 • Counters and Shift Registers

EXAMPLE 9.10

Write a VHDL file that instantiates a 12-bit LPM counter with asynchronous clear and syn-

chronous set functions. Design the counter to set to 2047 (decimal). Create a simulation to

verify the counter operation.

Solution The required VHDL file is:

——sset_lpm.vhd

——12-bit LPM counter with sset and aclr

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

LIBRARY lpm;

USE lpm.lpm_components.ALL;

ENTITY sset_lpm IS

PORT(

clk

: IN

STD_LOGIC;

clear, set : IN

STD_LOGIC;

q

: OUT STD_LOGIC_VECTOR (11 downto 0) );

END sset_lpm;

sset_lpm.vhd

sset_lpm.scf

(LPM_WIDTH => 12,

GENERIC MAP

LPM_SVALUE => “2047”)

PORT MAP ( clock

=>

clk,

sset

=>

set,

aclr

=>

clear,

q

=>

q);

END a;

Figure 9.56 shows the simulation file of the counter. The full count sequence would take over 160 s, so we will assume the count portion of the design works properly. Only the set and clear functions are fully simulated. The count waveform is shown in decimal.

FIGURE 9.56

Example 9.10

Simulation of a 12-bit Counter with Synchronous Set to 2047 and Asynchronous Clear

SECTION 9.6 REVIEW PROBLEM

9.6The first part of a VHDL process statement includes a sensitivity list: PROCESS (sensitivity list). How should this be written for a counter with asynchronous clear and for a counter with synchronous clear?

9.7 • Shift Registers

413

9.7 Shift Registers

K E Y T E R M S

Shift register A synchronous sequential circuit that will store and move n-bit data, either serially or in parallel, in n flip-flops.

SRGn Abbreviation for an n-bit shift register (e.g., SRG4 indicates a 4-bit shift register).

Serial shifting Movement of data from one end of a shift register to the other at a rate of one bit per clock pulse.

Parallel transfer Movement of data into all flip-flops of a shift register at the same time.

Rotation Serial shifting of data with the output(s) of the last flip-flop connected to the synchronous input(s) of the first flip-flop. The result is continuous circulation of the same data.

Right shift A movement of data from the left to the right in a shift register. (Right is defined in MAX PLUS II as toward the LSB.)

Left shift A movement of data from the right to the left in a shift register. (Left is defined in MAX PLUS II as toward the MSB.)

Bidirectional shift register A shift register that can serially shift bits left or right according to the state of a direction control input.

Parallel-load shift register A shift register that can be preset to any value by directly loading a binary number into its internal flip-flops.

Universal shift register A shift register that can operate with any combination of serial and parallel inputs and outputs (i.e., serial in/serial out, serial in/parallel out, parallel in/serial out, parallel in/parallel out). A universal shift register is often bidirectional, as well.

A shift register is a synchronous sequential circuit used to store or move data. It consists of several flip-flops, connected so that data are transferred into and out of the flip-flops in a standard pattern.

Figure 9.57 represents three types of data movement in three 4-bit shift registers. The circuits each contain four flip-flops, configured to move data in one of the ways shown.

Figure 9.57a shows the operation of serial shifting. The stored data are taken in one at a time from the input and moved one position toward the output with each applied clock pulse.

Parallel transfer is illustrated in Figure 9.57b. As with the synchronous parallel load function of a presettable counter, data move simultaneously into all flip-flops when a clock pulse is applied. The data are available in parallel at the register outputs.

Rotation, depicted in Figure 9.57c, is similar to serial shifting in that data are shifted one place to the right with each clock pulse. In this operation, however, data are continuously circulated in the shift register by moving the rightmost bit back to the leftmost flipflop with each clock pulse.

Serial Shift Registers

srg4_sr.gdf srg4_sr.scf

For a D flip-flop, Q follows D. The value of a bit stored in any flip-flop after a clock pulse is the same as the bit in the flip-flop to its left before the pulse. The result is that when a clock pulse is applied to the circuit, the contents of the flip-flops move one position to the

414 C H A P T E R 9 • Counters and Shift Registers

Q3

Q2

Q1

Q0

a. Serial shifting

Q3

Q2

Q1

Q0

b. Parallel transfer

Q3

Q2

Q1

Q0

c. Rotation

FIGURE 9.57

Data Movement in a 4-bit Shift Register

DFF

DFF

DFF

DFF

INPUT

PRN

Q3

PRN

Q2

PRN

Q1

PRN

Q0

Serial_in

D

Q

D

Q

D

Q

D

Q

CLRN

CLRN

CLRN

CLRN

INPUT

Clock

OUTPUT

Q0

OUTPUT

Q1

OUTPUT

Q2

OUTPUT

Q3

FIGURE 9.58

4-bit Serial Shift Register Configured to Shift Right

right and the bit at the circuit input is shifted into Q3. The bit stored in Q0 is overwritten by the former value of Q1 and is lost. Since the data move from left to right, we say that the shift register implements a right shift function. (Data movement in the other direction, requiring a different circuit connection, is called left shift.)

Let us track the progress of data through the circuit in two cases. All flip-flops are initially cleared in each case.

Case 1: A 1 is clocked into the shift register, followed by a string of 0s, as shown in Figure 9.59. The flip-flop containing the 1 is shaded.

Before the first clock pulse, all flip-flops are filled with 0s. Data In goes to a 1 and on the first clock pulse, the 1 is clocked into the first flip-flop. After that, the input goes to 0. The 1 moves one position right with each clock pulse, the register filling up with 0s behind it, fed by the 0 at Data In.After four clock pulses, the 1 reaches the Data Out flip-flop. On the fifth pulse, the 0 coming behind overwrites the 1 at Q0, leaving the register filled with 0s.

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