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9.9

•

Shift Register Counters

441

Clock

FIGURE 9.79

Circulating a 0 in a Ring Counter

442 C H A P T E R 9 • Counters and Shift Registers

FIGURE 9.80

Timing Diagrams for Figures 9.78 and 9.79

	0		0		0		0
D	Q3	D	Q2	D	Q1	D	Q0
D	Q	D	Q	D	Q	D	Q
	Q		Q		Q		Q

Clock

FIGURE 9.81

4-bit Johnson Counter

Table 9.17 Count Sequence of

a 4-bit Johnson Counter

Q3	Q2	Q1	Q0
0	0	0	0
1	0	0	0
1	1	0	0
1	1	1	0
1	1	1	1
0	1	1	1
0	0	1	1
0	0	0	1

counter.”

Figure 9.82 shows the progress of data through a Johnson counter that starts cleared (Q3Q2Q1Q0 0000). The shaded ﬂip-ﬂops represents 1s and the unshaded ﬂip-ﬂops are 0s.

Every 0 at Q0 is fed back to D3 as a 1 and every 1 is fed back as a 0. The count sequence for this circuit is given in Table 9.17. There are 8 unique states in the count sequence table.

443

Clock

FIGURE 9.82

Data Circulation in a 4-bit Johnson Counter

444 C H A P T E R 9 • Counters and Shift Registers

EXAMPLE 9.19

jnsn_ct.vhd jnsn_ct8.vhd jnsn_ct8.scf

Write the VHDL code for a Johnson counter of generic width and instantiate it as an 8-bit counter. List the sequence of states in a table, assuming the counter is initially cleared, and create a simulation to verify the circuit’s operation. Include a clear input (synchronous).

Solution The VHDL design entities for the generic-width component and the 8-bit Johnson counter follow.

——jnsn_ct.vhd

——Johnson counter of generic width LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

ENTITY jnsn_ct IS

GENERIC (width : POSITIVE := 4);

PORT (

clk, clr :		IN	STD_LOGIC;
q	:	BUFFER	STD_LOGIC_VECTOR(width-1 downto 0) );

END jnsn_ct;

_counter of jnsn_ct IS

BEGIN

IF (clk‘EVENT and clk = ‘1’) THEN

IF clr = ‘0’ THEN

q <= (others => ‘0’); —— n-bit clear function (n = width)

ELSE

q(width-1 downto 0) <= (not q(0) ) & q(width-1 downto 1);

END IF;

END PROCESS;

END johnson_counter;

——jnsn_ct8.vhd

——8-bit Johnson counter using component jnsn_ct LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

ENTITY jnsn_ct8 IS
PORT(
clock, clear : IN		STD_LOGIC;
qo	: BUFFER	STD_LOGIC_VECTOR(7 downto 0));
END jnsn_ct8;

ARCHITECTURE johnson_counter of jnsn_ct8 IS COMPONENT jnsn_ct GENERIC (width : POSITIVE);

PORT(
clk, clr : IN		STD_LOGIC;
q	: BUFFER	STD_LOGIC_VECTOR(7 downto 0) );
END COMPONENT;
BEGIN
johnson: jnsn_ct
GENERIC MAP (width=> 8)
PORT MAP (clk => clock
	clr => clear,
	q	=> qo);
END johnson_counter;

9.9 • Shift Register Counters

445

Table 9.18 Count Sequence of an 8-bit Johnson Counter

Q7Q6Q5Q4Q3Q2Q1Q0

00000000

10000000

11000000

11100000

11110000

11111000

11111100

11111110

11111111

01111111

00111111

00011111

00001111

00000111

00000011

00000001

Note that in the component ﬁle (jnsn_ct.vhd), the counter is cleared synchronously by the statement ( q <= (others => ‘0’);). Recall that the clause (others => ‘0’) can be used to set all bits of a signal aggregate to the value ‘0’. This is a simple way to clear a vector of unknown width without using a conversion function.

Table 9.18 shows the count sequence for the 8-bit Johnson counter.

The simulation of the Johnson counter, including one full cycle and a clear, is shown in Figure 9.83.

FIGURE 9.83

Example 9.19

Simulation of an 8-bit Johnson

Counter

Johnson Counter Modulus and Decoding

N O T E

The maximum modulus of a Johnson counter is 2n for a circuit with n ﬂip-ﬂops.

The Johnson counter represents a compromise between binary and ring counters, whose maximum moduli are, respectively, 2n and n for an n-bit counter.