Файл: Digital design with CPLD applications and VHDL (R. Dueck, 2000).pdf
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9.8 • Programming Shift Registers in VHDL |
431 |
WHEN ‘1’ =>
q <= rsi & q(3 downto 1); —— right shift WHEN others =>
NULL;
END CASE;
END IF;
END PROCESS;
END bidirectional_shift;
Figure 9.73 shows the simulation of the shift register, with the left shift function in the first half of the simulation and the right shift function in the second half.
FIGURE 9.73
Example 9.15
4-bit Bidirectional Shift Register
Shift Registers of Generic Width
K E Y T E R M
GENERIC A clause in the entity declaration of a VHDL component that lists the
parameters that can be specified when the component is instantiated.
All multibit VHDL components we have examined until now have been of a specified width (e.g., 2-to-4 decoder, 8-bit MUX, 8-bit adder, 4-bit counter). VHDL allows us to create components having a generic, or unspecified, width or other parameter which is specified when the component is instantiated. In the entity declaration of such a component, we indicate an unspecified parameter (such as width) in a GENERIC clause. The unspecified parameter must be given a default value in the GENERIC clause, indicated by : value.
When we instantiate the component, we specify the parameter value in a generic map, as we have done with components from the Library of Parameterized Modules. The design entity srt_bhv.vhd below behaviorally defines an n-bit right-shift register, with a default width of four bits given by the statement ( GENERIC (width : POSITIVE := 4);).
The entity srt8_bhv.vhd instantiates the n-bit register as an 8-bit circuit by specifying the bit width in a generic map. If no value is specified, the component is presumed to have a default width of four, as defined in the component’s entity declaration.
—— srt_bhv.vhd
434 |
C H A P T E R 9 • Counters and Shift Registers |
||
rsi, lsi |
: IN STD_LOGIC; |
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function_select |
: IN STD_LOGIC_VECTOR(1 downto 0); |
||
p |
: IN STD_LOGIC_VECTOR(width-1 downto 0); |
||
q |
: BUFFER STD_LOGIC_VECTOR(width-1 downto 0)); |
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END COMPONENT; |
|||
BEGIN |
|||
Shift_universal_16: srg_univ |
|||
GENERIC MAP (width=> 16) |
|||
PORT MAP (clk |
=> clock, |
||
clear |
=> |
clr, |
|
rsi |
=> |
rsi, |
|
lsi |
=> |
lsi, |
|
function_select => |
s, |
||
p |
=> |
parallel_in, |
|
q |
=> |
qo); |
|
END universal_shift;
When we are designing the clear function in srg_univ.vhd, we must account for the fact that we must set all bits of a vector of unknown width to ‘0’. To get around this problem, we use a conversion function that changes an INTEGER value of 0 to a STD_LOGIC_VECTOR of width bits and assigns the value to the output. The required conversion function, CONV_STD_LOGIC_VECTOR(value, number_of_bits), is found in the std_logic_arith package in the ieee library. We could also use the construct
q <= (others => ‘0’);
which states that the default case is to set all bits of q to 0 when clear is 0. Since there is no other case specified, all bits of q are cleared.
LPM Shift Registers
The Library of Parameterized Modules contains a shift register component, lpm_shiftreg, that we can instantiate in a VHDL design entity. The various functions of lpm_shiftreg are listed in Table 9.16.
The following VHDL code instantiates lpm_shiftreg as an 8-bit shift register with serial input and serial output. In this case, the LPM component is declared explicitly, with the component declaration statement listing only the ports and parameters used by the design entity. The component instantiation statement lists the port names from the design entity in the same order as the corresponding component port names. By default the register direction is LEFT (i.e., toward the MSB).
——srg8_lpm.vhd
——8-bit serial shift register (shift left by default) LIBRARY ieee;
USE ieee.std_logic_1164.ALL; LIBRARY lpm;
USE lpm.lpm_components.ALL;