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			9.8 • Programming Shift Registers in VHDL	435
Table 9.16 Available Functions for lpm_shiftreg

Function	Ports	Parameters	Description

Basic serial operation	clock, shiftin,	LPM_WIDTH	Data moves serially from shiftin to shiftout. Parallel outputs
	shiftout, q[]		appear at q[].

Load	sload, data[]	none	When sload 1, q[] goes to the value at input data[] on the
			next positive clock edge. Data[] has the same width as
			LPM_WIDTH.

Synchronous clear	sclr	none	When sclr 1, q[] goes to zero on positive clock edge

Synchronous set	sset	LPM_SVALUE	When sset 1, output goes to value of LPM_SVALUE on
			positive clock edge. If LPM_SVALUE is not speciﬁed q[]
			goes to all 1s.

Asynchronous clear	aclr	none	Output goes to zero when aclr 1.

Asynchronous set	aset	LPM_AVALUE	Output goes to value of LPM_AVALUE when aset 1.
			If LPM_AVALUE is not speciﬁed, outputs all go HIGH
			when aset 1.

Directional control	none	LPM_DIRECTION	Optional direction control. Default direction is LEFT.
			LPM_DIRECTION “LEFT” or “RIGHT”.
			If shiftin and shiftout are used, the serial shift always goes
			through the entire shift register, in the direction given by
			LPM_DIRECTION.

Clock enable	enable	none	All synchronous functions are enabled when enable 1.
			Defaults to “enabled” when not speciﬁed.

srg8_lpm.vhd srg8_lpm.scf

ENTITY srg8_lpm IS

PORT (

clk : IN STD_LOGIC; serial_in : IN STD_LOGIC; serial_out : OUT STD_LOGIC);

COMPONENT lpm_shiftreg

GENERIC(LPM_WIDTH: POSITIVE);

PORT (

clock, shiftin	: IN STD_LOGIC;
shiftout	: OUT STD_LOGIC);
END COMPONENT;
BEGIN
Shift_8: lpm_shiftreg

GENERIC MAP (LPM_WIDTH=> 8)

PORT MAP (clk, serial_in, serial_out);

END lpm_shift;

Figure 9.74 shows a simulation of the shift register, with the data shifting from right to left (LSB to MSB). Since there is no parallel output (q[]) instantiated in our design, we would not normally be able to monitor the progress of bits from ﬂip-ﬂop to ﬂip-ﬂop; we would only see shiftin, and then, eight clock cycles later, shiftout. However, we are able to monitor the ﬂip-ﬂop states as buried nodes (Shift_8|dffs[7..0].Q). These buried nodes are the last eight lines in the simulation.

436 C H A P T E R 9 • Counters and Shift Registers

FIGURE 9.74

Simulation of an 8-bit LPM Shift

9.17Modify the VHDL code just shown to make the serial shift register shift right, rather than left. Create a simulation to verify the circuit function. How do the positions of shiftin and shiftout ports relate to the internal ﬂip-ﬂops for the right-shift and left-shift implementations?

Solution The modiﬁed VHDL code is shown next as design entity srg8lpm2. The only difference is the addition of the parameter LPM_DIRECTION to both the component declaration and component instantiation statements.

——srg8_lpm2.vhd

——8-bit serial shift register (shift right)

srg8_lpm2.vhd srg8_lpm2.scf

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

LIBRARY lpm;

USE lpm.lpm_components.ALL;

ENTITY srg8lpm2 IS

PORT (

clk : IN STD_LOGIC; serial_in : IN STD_LOGIC; serial_out : OUT STD_LOGIC);

END srg8_lpm2;

ARCHITECTURE lpm_shift of srg8_lpm2 IS

COMPONENT lpm_shiftreg

GENERIC(LPM_WIDTH: POSITIVE; LPM_DIRECTION: STRING); PORT (

clock, shiftin : IN STD_LOGIC;

shiftout	: OUT STD_LOGIC);
END COMPONENT;

BEGIN

shift_8: lpm)_shiftreg

GENERIC MAP (LPM_WIDTH=> 8, LPM_DIRECTION => “RIGHT”) PORT MAP (clk, serial_in, serial_out);

END lpm_shift;

9.8 • Programming Shift Registers in VHDL

437

FIGURE 9.75

Example 9.17

Simulation of an 8-bit LPM Shift

The simulation for the right-shift register is shown in Figure 9.75. The inputs are identical to those of Figure 9.74, but the internal shift direction is opposite. The LPM component conﬁgures the serial shift input and output such that they allow data to go through the entire register, regardless of shift direction. For left-shift, serial_in (shiftin) is applied to D0, and is shifted toward Q7. For right-shift, the same serial_in is applied to D7 and shifted toward Q0. Thus, there is no right shift input or left shift input in this component, and also no bidirectional shift that can be controlled by an input port. Shift direction can only be set by the value of a parameter and is therefore ﬁxed when a component is instantiated.

9.18Write the VHDL code for an 8-bit LPM shift register with both parallel and serial outputs, parallel load and asynchronous clear. Create a simulation to verify the design operation.

Solution The VHDL code for the parallel load shift register follows as srg8lpm3.

LIBRARY ieee;

USE ieee.std_logic_1164.ALL; LIBRARY lpm;

USE lpm.lpm_components.ALL;

srg8lpm3.vhd

srg8lpm3.scf

ENTITY srg8lpm3 IS
PORT (
clk, ld, clr	: IN	STD_LOGIC;
p	: IN	STD_LOGIC_VECTOR(7 downto 0);
q_out	: OUT	STD_LOGIC_VECTOR(7 downto 0);
serial_out	: OUT	STD_LOGIC);
END srg8lpm3;

ARCHITECTURE lpm_shift of srg8lpm3 IS

COMPONENT lpm_shiftreg

GENERIC(LPM_WIDTH: POSITIVE);

PORT (

clock, load	: IN	STD_LOGIC;
aclr	: IN	STD_LOGIC;
data	: IN	STD_LOGIC_VECTOR (7 downto 0);
q	: OUT	STD_LOGIC_VECTOR (7 downto 0);
shiftout	: OUT	STD_LOGIC);
END COMPONENT;
BEGIN

438 C H A P T E R 9 • Counters and Shift Registers

Shift_8: lpm_shiftreg

GENERIC MAP (LPM_WIDTH=> 8)

PORT MAP (clk, ld, clr, p, q_out, serial_out);

END lpm_shift;

The simulation for srg8lpm3 is shown in Figure 9.76. The load input is initially HIGH, causing the shift register to load 55H ( 01010101) on the ﬁrst clock pulse. Since we have not instantiated the serial input shiftin, the serial input reverts to a default value of ‘1’, causing the register to be ﬁlled with 1s. If we did not want this to be the case, we

would have to instantiate the shiftin port and set it to ‘0’.

FIGURE 9.76

Example 9.18

Simulation of an 8-bit LPM Shift

SECTION 9.8 REVIEW PROBLEM

9.8When a shift register is encoded in VHDL, why are its outputs deﬁned as BUFFER, not OUT?

9.9Shift Register Counters

K E Y T E R M S

Ring counter A serial shift register with feedback from the output of the last ﬂipﬂop to the input of the ﬁrst.

Johnson counter A serial shift register with complemented feedback from the output of the last ﬂip-ﬂop to the input of the ﬁrst. Also called a twisted ring counter

By introducing feedback into a serial shift register, we can create a class of synchronous counters based on continuous circulation, or rotation, of data.

If we feed back the output of a serial shift register to its input without inversion, we create a circuit called a ring counter. If we introduce inversion into the feedback loop, we have a circuit called a Johnson counter. These circuits can be decoded more easily than binary counters of similar size and are particularly useful for event sequencing.

Ring Counters

9.9 • Shift Register Counters

439

Figure 9.77 shows a 4-bit ring counter made from D ﬂip-ﬂops. This circuit could also be constructed from SR or JK ﬂip-ﬂops, as can any serial shift register.

A ring counter circulates the same data in a continuous loop. This assumes that the

FIGURE 9.77

4-bit Ring Counter

Clock

data have somehow been placed into the circuit upon initialization, usually by synchronous or asynchronous preset and clear inputs, which are not shown.

Figure 9.78 shows the circulation of a logic 1 through a 4-bit ring counter. If we assume that the circuit is initialized to the state Q3Q2Q1Q0 1000, it is easy to see that the 1 is shifted one place right with each clock pulse. The feedback connection from Q0 to D3 ensures that the input of ﬂip-ﬂop 3 will be ﬁlled by the contents of Q0, thus recirculating the initial data. The ﬁnal transition in the sequence shows the 1 recirculated to Q3.

A ring counter is not restricted to circulating a logic 1. We can program the counter to circulate any data pattern we happen to ﬁnd convenient.

Figure 9.79 shows a ring counter circulating a 0 by starting with an initial state of Q3Q2Q1Q0 0111. The circuit is the same as before; only the initial state has changed. Figure 9.80 shows the timing diagrams for the circuit in Figures 9.78 and 9.79.

Ring Counter Modulus and Decoding

The maximum modulus of a ring counter is the maximum number of unique states in its count sequence. In Figures 9.78 and 9.79, the ring counters each had a maximum modulus of 4. We say that 4 is the maximum modulus of the ring counters shown, since we can change the modulus of a ring counter by loading different data at initialization.

For example, if we load a 4-bit ring counter with the data Q3Q2Q1Q0 1000, the following unique states are possible: 1000, 0100, 0010, and 0001. If we load the same circuit with the data Q3Q2Q1Q0 1010, there are only two unique states: 1010 and 0101. Depending on which data are loaded, the modulus is 4 or 2.

Most input data in this circuit will yield a modulus of 4. Try a few combinations.

N O T E

The maximum modulus of a ring counter is the same as the number of bits in its output.

A ring counter requires more ﬂip-ﬂops than a binary counter to produce the same number of unique states. Speciﬁcally, for n ﬂip-ﬂops, a binary counter has 2n unique states and a ring counter has n.

This is offset by the fact that a ring counter requires no decoding. A binary counter used to sequence eight events requires three ﬂip-ﬂops andeight 3-input decoding gates. To perform the same task, a ring counter requires eight ﬂip-ﬂops and no decoding gates.

As the number of output states of an event sequencer increases, the complexity of the decoder for the binary counter also increases. A circuit requiring 16 output states can be implemented with a 4-bit binary counter and sixteen 4-input decoding gates. If you need 18 output states, you must have a 5-bit counter (24 18 25) and eighteen 5-input decoding gates.

The only required modiﬁcation to the ring counter is one more ﬂip-ﬂop for each addi-

440 C H A P T E R 9 • Counters and Shift Registers

Clock

FIGURE 9.78

Circulating a 1 in a Ring Counter

tional state. A 16-state ring counter needs 16 ﬂip-ﬂops and an 18-state ring counter must have 18 ﬂip-ﬂops. No decoding is required for either circuit.

Johnson Counters

Figure 9.81 shows a 4-bit Johnson counter constructed from D ﬂip-ﬂops. It is the same as a ring counter except for the inversion in the feedback loop where Q0 is connected to D3. The circuit output is taken from ﬂip-ﬂop outputs Q3 through Q0. Since the feedback introduces a “twist” into the recirculating data, a Johnson counter is also called a “twisted ring

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