Файл: Digital design with CPLD applications and VHDL (R. Dueck, 2000).pdf

the present state is 010, the next state is not 011, as we would expect, but 110, which we derive by examining the state diagram.

Why list the present states in binary order, rather than the same order as the output sequence? By doing so, we can easily simplify the equations for the D inputs of the flipflops by using a series of Karnaugh maps. This is still possible, but harder to do, if we list the present states in order of the output sequence.

4.Use flip-flop excitation tables to determine at what states the flip-flop synchronous inputs must be to make the circuit go from each present state to its next state. This is not necessary if we use D flip-flops, since Q follows D. The D inputs are the same as the next state outputs. For JK or T flip-flops, we would follow the same procedure as for the design of synchronous counters outlined in Chapter 9.

5.Simplify the Boolean expression for each synchronous input. Figure 10.5 shows three Karnaugh maps, one for each D input of the circuit.

FIGURE 10.5

Karnaugh Maps for 3-bit Gray Code Counter

The K-maps yield three Boolean equations:

D2 Q1Q0 Q2Q0

D1 Q1Q0 Q2Q0

D0 Q2 Q1 Q2Q1

6.Draw the logic circuit for the state machine. Figure 10.6 shows the circuit for a 3-bit Gray code counter, drawn as a Graphic Design File in MAX PLUS II. A simulation for this circuit is shown in Figure 10.7, with the outputs shown as individual waveforms and as a group with a binary value.

462

FIGURE 10.6

Logic Diagram of a 3-bit Gray Code Counter

gray_ct3.gof gray_ct3.scf

FIGURE 10.7

Simulation of a 3-bit Gray Code Counter (from Graphic Design File)

VHDL Design of State Machines

K E Y T E R M S

Enumerated type A user-defined type in VHDL in which all possible values of a

named identifier are listed in a type definition statement.

State machines can be defined in VHDL within a CASE statement. The VHDL code below illustrates the principle, using the 3-bit Gray code counter as an example.

––gray_ct1.vhd

––3-bit Gray code counter

––(state machine with decoded outputs)

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

END gray_ct1;

s6, s7);

gray_ct1.vhd

BEGIN

PROCESS (clk)

BEGIN

IF clk’EVENT AND clk = ‘1’ THEN

CASE state IS

WHEN s0 => state <= s1;

WHEN s1 => state <= s2;

WHEN s2 => state <= s3;

WHEN s3 => state <= s4;

WHEN s4 => state <= s5;

IF (x=‘0’ and y=‘0’) THEN

position <= down;

ELSIF (x=‘0’ and y=‘1’) THEN

position <= left;

ELSIF (x=‘1’ and y=‘0’) THEN

position <= up;

ELSE

position <= right;

END IF;

Thus the named identifier position of type DIRECTION can take on only the four values specified in the enumerated type definition.

An alternative way to encode the 3-bit counter is to include output assignments within the body of the CASE statement. Each case then has more than one statement, as indicated in the following VHDL code.

-- gray_ct2.vhd

-- 3-bit Gray code counter

-- (outputs defined within states)

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

ENTITY gray_ct2 IS

ARCHITECTURE a OF gray_ct2 IS

TYPE STATE_TYPE IS (s0, s1, s2, s3, s4, s5, s6, s7);

SIGNAL state: STATE_TYPE;

BEGIN

PROCESS (clk)

BEGIN

IF clk’EVENT AND clk = ‘1’ THEN