Файл: Digital design with CPLD applications and VHDL (R. Dueck, 2000).pdf

466 C H A P T E R 1 0 • State Machine Design

state <= s0;

q <= “000”;

END CASE;

END IF;

END PROCESS;

END a;

The above VHDL code is identical to that of the previous example, except for the way the outputs are assigned.

SECTION 10.2 REVIEW PROBLEM

10.2Write the Boolean equations for the J and K inputs of the flip-flops in a 3-bit Gray code counter based on JK flip-flops.

10.3State Machines with Control Inputs

K E Y T E R M S

Control input A state machine input that directs the machine from state to state.

Conditional transition A transition between states of a state machine that occurs only under specific conditions of one or more control inputs.

Unconditional transition A transition between states of a state machine that occurs regardless of the status of any control inputs.

As an extension of the techniques used in the previous section, we will examine the design of state machines that use control inputs, as well as the clock, to direct their operation. Outputs of these state machines will not necessarily be the same as the states of the machine’s flip-flops. As a result, this type of state machine requires a more detailed state diagram notation, such as that shown in Figure 10.8.

The state machine represented by the diagram in Figure 10.8 has two states, and thus

requires only one state variable. Each state is represented by a bubble (circle) containing the state name and the value of the state variable. For example, the bubble containing the

notation start indicates that the state called start corresponds to a state variable with a

0

value of 0. Each state must have a unique value for the state variable(s).

Transitions between states are marked with a combination of input and output values

corresponding to the transition. The inputs and outputs are labeled in1, in2, . . . , inx/out1, out2, . . . ,outx. The inputs and outputs are sometimes simply indicated by the value of each variable for each transition. In this case, a legend indicates which variable corresponds to which position in the label.

For example, the legend in the state diagram of Figure 10.8 indicates that the inputs and outputs are labeled in the order in1/out1, out2. Thus if the machine is in the start state and the input in1 goes to 0, there is a transition to the state continue. During this transition, out1 goes to 1 and out2 goes to 0. This is indicated by the notation 0/10 beside the transitional arrow. This is called a conditional transition because the transition depends on the state of in1. The other possibility from the start state is a no-change transition, with both outputs at 0, if in1 1. This is shown as 1/00.

If the machine is in the state named continue, the notation X/01 indicates that the machine makes a transition back to the start state, regardless of the value of in1, and that out1 0 and out2 1 upon this transition. Since the transition always happens, it is called an unconditional transition.

What does this state machine do? We can determine its function by analyzing the state diagram, as follows.

1.There are two states, called start and continue. The machine begins in the start state and waits for a LOW input on in1. As long as in1 is HIGH, the machine waits and the outputs out1 and out2 are both LOW.

2.When in1 goes LOW, the machine makes a transition to continue in one clock pulse. Output out1 goes HIGH.

3.On the next clock pulse, the machine goes back to start. The output out2 goes HIGH and out1 goes back LOW.

4.If in1 is HIGH, the machine waits for a new LOW on in1. Both outputs are LOW again. If in1 is LOW, the cycle repeats.

In summary, the machine waits for a LOW input on in1, then generates a pulse of one clock cycle duration on out1, then on out2. A timing diagram describing this operation is shown in Figure 10.9.

CLK

in1

out1

out2

start start

continue

FIGURE 10.9

Ideal Operation of State Machine in Figure 10.8

Classical Design of State Machines with Control Inputs

We can use the classical design technique of the previous section to design a circuit that implements the state diagram of Figure 10.8.

1.Define the problem. Implement a digital circuit that generates a pulse on each of two outputs, as described above. For this implementation, let us use JK flip-flops for the state logic. If we so chose, we could also use D or T flip-flops.

2.Draw a state diagram. The state diagram is shown in Figure 10.8.