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470 C H A P T E R 1 0 • State Machine Design

FIGURE 10.13

Simulation of the State Machine of Figure 10.12

The VHDL code for the state machine implemented above is as follows.

--state_x1.vhd

--state machine example 1

--Two states, one input, two outputs

--Generates a pulse on one output, then the next

--after receiving a LOW on the input

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

state_x1.vhd state_x1.scf

ENTITY state_x1 IS

PORT(

clk, in1 : IN STD_LOGIC; out1, out2 : OUT STD_LOGIC);

END state_x1;

ARCHITECTURE a OF state_x1 IS

TYPE PULSER IS (start, continue);

SIGNAL sequence: PULSER;

BEGIN

PROCESS (clk)

THEN

WHEN start =>

IF in1 = ‘1’ THEN

sequence <= start; -- no change if in1 1 out1 <= ‘0’;

out2 <= ‘0’;

ELSE

sequence <= continue; -- proceed if in1 0

out1 <= ‘1’;

-- pulse on out1

out2 <= ‘0’;

END IF;

WHEN continue =>

sequence <= start;

out1 <= ‘0’;

out2 <= ‘1’;

-- pulse on out2

END CASE;

END IF;

END PROCESS;

END a;

10.3 • State Machines with Control Inputs

471

The transition from start is conditional, so the case for start contains an IF statement that defines the possible state transitions and their associated output states. The transition from continue is unconditional, so no IF statement is needed in the corresponding case.

Figure 10.14 shows the simulation for the VHDL design entity, state_x1.vhd. The values of the state variable, sequence, are also shown in the simulation. This gives us a ready indication of the machine’s state (start or continue).

FIGURE 10.14

Simulation of the State Machine in VHDL Entity state_x1

The design of the state machine is such that if the input in1 is held LOW beyond the end of one pulse cycle, the cycle will repeat, as shown in the simulation of Figure 10.15.

FIGURE 10.15

Simulation of VHDL State Machine Showing a Repeated Output Cycle

EXAMPLE 10.1

A state machine called a single-pulse generator operates as follows:

1.

The circuit has two states: seek and find, an input called sync and an output called

pulse.

2.

The state machine resets to the state seek. If sync 1, the machine remains in seek and

Application

the output, pulse, remains LOW.

3.

When sync 0, the machine makes a transition to find. In this transition, pulse goes

HIGH.

4.

When the machine is in state find and sync 0, the machine remains in find and pulse

goes LOW.

5.

When the machine is in find and sync 1, the machine goes back to seek and pulse re-

mains LOW.

Use classical state machine design techniques to design the circuit for the single-pulse

generator, using D flip-flops for the state logic. Use MAX PLUS II to draw the state

472 C H A P T E R 1 0 • State Machine Design

machine circuit. Create a simulation to verify the design operation. Briefly describe what this state machine does.

Solution Figure 10.16 shows the state diagram derived from the description of the state machine. The state table is shown in Table 10.5. Since Q follows D, the D input is the same as the next state of Q.

FIGURE 10.16

Example 10.1

1/0

State Diagram for a Single-pulse

sync/pulse

Generator

seek

0

0/1

1/0

find 1

0/0

pulse1.gdf

pulse1.scf

Table 10.5 State Table for Single-Pulse Generator

Present State

Input

Next State

Sync. Input

Output

Q

sync

Q

D

pulse

0

0

1

1

1

0

1

0

0

0

1

0

1

1

0

1

1

0

0

0

output equations are:

D Q sync Q sync sync pulse Q sync

Figure 10.17 shows the state machine circuit derived from the above Boolean equations. The simulation for this circuit is shown in Figure 10.18. The simulation shows that the circuit generates one pulse when the input sync goes LOW, regardless of the length of time that sync is LOW. The circuit could be used in conjunction with a debounced pushbutton to produce exactly one pulse, regardless of how long the pushbutton was held down. Figure 10.19 shows such a circuit.

DFF

AND2

NOT

NOT

OUTPUT

SYNC

INPUT

D

PRN

PULSE

Q

CLK

INPUT

CLRN

FIGURE 10.17

Example 10.1

Single-pulse Generator

10.3 • State Machines with Control Inputs

473

FIGURE 10.18

Example 10.1

Simulation of a Single-pulse Generator (from GDF)

Vcc

Single-pulse

generator

Debouncer

SYNC

N.O.

CLK

PULSE

FIGURE 10.19

Example 10.1

Single-pulse Generator Used with a Debounced Pushbutton

EXAMPLE 10.2

The state machine of Example 10.1 is vulnerable to asynchronous input changes. How do

we know this from the circuit schematic and from the simulation waveform? Modify the

circuit to eliminate the asynchronous behavior and show the effect of the change on a sim-

ulation of the design. How does this change improve the design?

Solution The output, pulse, in the state machine of Figure 10.17 is derived from the

state flip-flop and the combinational logic of the circuit. The output can be affected by a

change that is purely combinational, thus making the output asynchronous. This is demon-

strated on the first pulse of the simulation in Figure 10.18, where pulse momentarily goes

HIGH between clock edges. Since no clock edge was present when either the input, sync,

changed or when pulse changed, the output pulse must be due entirely to changes in the

combinational part of the circuit.

The circuit output can be synchronized to the clock by adding an output flip-flop, as in

Figure 10.20. A simulation of this circuit is shown in Figure 10.21. With the synchronized

output, the output pulse is always the same width: one clock period. This gives a more pre-

dictable operation of the circuit.

DFF

DFF

NOT

NOT

AND2

PRN

PRN

OUTPUT

SYNC

INPUT

D

Q

PULSE

D

Q

CLRN

CLRN

INPUT

CLK

FIGURE 10.20

Example 10.2

Single-pulse Generator with Synchronous Output

474 C H A P T E R 1 0 • State Machine Design

pulse1a.gdf

pulse1a.scf

FIGURE 10.21

Example 10.2

Simulation of a Single-pulse Generator with Synchronous Output (from GDF)

10.3Write the VHDL code for a design entity that implements the single-pulse generator, as described in Example 10.1. Create a simulation that verifies the operation of the design.

Solution The required VHDL code is given here in the design entity sngl_pls.

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

sngl_pls.vhd sngl_pls.scf

ENTITY sngl_pls IS

PORT(

clk, sync : IN STD_LOGIC; pulse : OUT STD_LOGIC);

END sngl_pls;

BEGIN

PROCESS (clk, sync)

BEGIN

IF (clk‘EVENT and clk = ‘1’) THEN

CASE status IS

WHEN seek =>

IF (sync = ‘1’) THEN

status <= seek;

pulse <= ‘0’;

ELSE

status <= find;

pulse <= ‘1’;

END IF;

WHEN find =>

IF (sync = ‘1’) THEN

status <= seek;

pulse <= ‘0’;

ELSE

status <= find;

pulse <= ‘0’;

END IF;

END CASE;

END IF;

END PROCESS;

END pulser;

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