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151CHAPTER SEVEN

Programmable Logic Devices

Programmable Logic Arrays

The PLA is a very flexible logic device, as it allows both the AND as well as the OR arrays to be programmed by the user. Figure 7-4 illustrates the architecture of a typical PLA.

The PLA allows the implementation of almost any sum-of-products logic function to be implemented, within the constraints of the available number of input pins, AND gates, OR gates, and output pins. While the PLA architecture allows more efficient utilization of the resources on the chip, it is also more difficult to program, as fuses must be programmed in two separate arrays. Standard memory programming devices cannot be easily modified to program a PLA with two arrays.

PLA — 4 IN - 4 OUT - 16 Products

13

12

11

10

OR Array

(Programmable)

X

X

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AND Array (Programmable)

X = Fuse-Link Crosspoint Connection

Q3

Q2

Q1

Q0

Figure 7-4: Typical PLA architecture.

PAL-Style PLDs

While there is a wide variety of programmable logic available, the most prevalent low cost version used in embedded designs is the PAL, a variation of the PLA sum-of-products chip. Consisting of a programmable AND (product) array and a factory-defined OR (sum) array, it is very similar to a standard memory device. As a result, many memory programmers can also be used to program PALs. This is a key reason for the success of these devices, along with the availability of software to ease in designing the fuse patterns for implementing specific users designs.

In a typical PAL, the inputs and their logical complements are provided to each of the AND gates through a programmable array of fuse connections.

152EMBEDDED CONTROLLER

Hardware Design

The connections between the AND and OR gates are fixed by the manufacturer, and in most cases, some of the outputs are also fed back to the input array. Figure 7-5 shows the

PAL implementation

A + B

A

Fuse-Link

of the logic function

Fuse-Link

Blown

Not Blown

/(A * /B + /A * B).

A + B

B

Figure 7-6 shows a simplified example of the logic and fuse configuration used in most PAL devices. It has four inputs and four outputs which are non-inverting sums of four products.

A

A

B

B

A

A + B

X

X

A + B

X

X

B

Figure 7-5: Example of PAL fuse programming.

PLA — 4 IN - 4 OUT - 16 Products

13

12

11

10

OR Array (Fixed)

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AND Array (Programmable)

X = Fuse-Link Crosspoint Connection

Q3 Q2 Q1 Q0

• = Fixed Connection

Figure 7-6: Typical PAL organization.

Most small PLD parts use a numbering convention that makes it easier to determine the configuration of the logic. The number is usually composed of three parts: the number of inputs to the array, output circuit type, and number of outputs. Thus a PAL with the part number 16L8 has 16 inputs to the AND array (not necessarily that many input pins), and eight active low outputs (L), while a 12H6 has 12 inputs, and six active high

(H) outputs. A device number with an “R” in it has an output register, and a “V” indicates variable or user programmable outputs. Some of the pins may

153CHAPTER SEVEN

Programmable Logic Devices

be shared inputs and outputs. Not all of the outputs are necessarily of the same type, however. The 16R4, for example, has four registered outputs and four asynchronous (un-registered) outputs. The V parts have a special output “macro-cell” that can be programmed to be asynchronous (un-clocked), synchronous (clocked), inverted, non-inverted, feedback internally to the AND array, and so on.

Design Examples

Probably the most common applications of simple PLDs are as address decoders in microcomputer and microprocessor systems. A device such as the 16L8 PAL, with active low outputs is well suited to drive the active low enable inputs of most memory and I/O

devices. Because a PAL

PLD

EPROM1CE

8031

EPROM2CE

can have different logic

PSEN

IN_EN

+V

functions on the same

RD

RAM1CE

chip, one PAL can

WR

RAM2CE

decode both memory

A15..A8

D0

SW1

and I/O addresses.

OUT_CK

Input Port

Figure 7-7 shows an

Address

16

+V

example of this. The

A0 ..15

A0 ..15

Output Port

program memory

RD

To RAM OE

C

LED

map for Figure 7-7 is

WR

To RAM WE

D0

D

Q

shown in Table 7-1; the

external data memory

Figure 7-7: PLD decoding of memory and I/O enables.

map is given in Table

7-2. Address and control lines

Program Memory Address Space

can be wired to the input pins,

Address Range (hex)

Device Selected

and the output pins can drive

Program 0000 - 7FFF

2Kx8 EPROM 1

the select and enable lines of

Program 8000 – FFFF

32Kx8 EPROM 2

the memory and I/O chips.

Table 7-1: Program memory map for Figure 7-7.

External Data Memory Address Space

Address Range (hex)

Device Selected

Table 7-2: External data

Data 0000

- 7FFF

32Kx8 SRAM 1

memory map for Figure 7-7.

Data 8000

- FEFF

32Kx8 SRAM 2

Data FF00 - FFFF Read

Input port enable

Data FF00 - FFFF Write

Output port latch clock
Figure 7-8: EPROM chip enable gate equivalents.
EPROM2CE
PSEN
A15
EPROM1CE
PSEN
A15

154EMBEDDED CONTROLLER

Hardware Design

An 8031 system with two program EPROMs, two data SRAMs, and memory mapped I/O ports could be connected using gates or decoders, but it would be more efficient to use a 16L8 PAL. The inputs to the PAL are the control and address lines. The outputs are the memory chip enables, the input port drive enable, and the output latch clock.

Note that the program memory is full, using two 32-kilobyte devices. Also, the input and output ports appear in the external memory address space. This is an example partially decoded, memory mapped I/O, since the input and output devices appear repeatedly in a memory address range of FF00 to FFFF hex.

For the program memory, the equations that must be used to program the PLD would be as follows:

/EPROM1CE = /PSEN * /A15 Enabled when PSEN active and A15 = 0 /EPROM2CE = /PSEN * A15 Enabled when PSEN active and A15 = 1

The equations above will enable the EPROMs when the processor is fetching instructions (/PSEN = 0) so that EPROM1 will be enabled for program memory addresses 0-7FFF and EPROM2 will be enabled for addresses 8000-FFFF.

The gates in Figure 7-8 are the equivalent to the equations for the EPROM chip enable equations shown above. Note that the gate used for the EPROM1CE function is equivalent to a simple OR

gate. This is because inverting all the inputs and outputs of a logic function

changes it from an AND to an OR and vice versa.

The RAM addresses are similarly

enabled when the processor is accessing external data memory, except that the input and output ports are memory mapped into addresses FF00 to FFFF. In order to avoid bus contention, SRAM 2 is disabled between FF00 and FFFF.

/RAM1CE = /A15 Enabled when A15 = 0 /RAM2CE = A15 * /A14 * /A13 * /A12 * /A11 * /A10 * /A9 * /A8

Enabled when address > 8000 and < FFxx

/IN_EN = /RD * A15 * A14 * A13 * A12 * A11 * A10 * A9 * A8 Input Enabled when RD low and address = FFxx

/OUT_CK = /WR * A15 * A14 * A13 * A12 * A11 * A10 * A9 * A8 Output latch clock when WR address FFxx

EPROM1
0000
Figure 7-9: Memory address map.
8000
7FFF
SRAM1
SRAM2
EPROM2

155CHAPTER SEVEN

Programmable Logic Devices

This PLD implements a system with 64 kilobytes of program EPROM, and 64 kilobytes-256 bytes of data RAM. Note that 256 bytes of the external data memory address space are dedicated, or mapped, to the input/output port. The input port can be read as if it were data memory at locations FF00 to FFFF hex. This incomplete, or partial address decoding, decodes 256 different addresses to access the same input/output port (partial I/O address decoding). Similarly, the output port can be written to by writing data to data RAM addresses FF00 to FFFF hex. Note that changing the I/O addresses to different values requires only changing the equations and burning the corresponding fuse map patterns into another PLD. If the address map should need to be changed, it is possible

to do so by using a different PAL

Program

External

device programmed with a

Data

different fuse map representing

Memory

Memory

FFFF

FFFF

I/O

different equations.

FF00

FEFF

Tables 7-1 and 7-2 above can also be represented graphically with an address map, as shown in Figure 7-9.

8000

7FFF

0000

PLD Development Tools

Because of the complexity that results from flexibility in defining PLD functions, it is not practical to manually define the fuse map that is used to program a PLD. Automated translation programs are used to convert a higherlevel description of the logic to the low-level fuse map that is required. The software that performs that task is referred to as a PLD assembler or compiler because it is equivalent to a programming language translator used on a general-purpose desktop personal computer. PLD development software is available from both PLD vendors and other software houses, in versions that run on PCs and workstations. PLD assemblers input Boolean equations and generate the corresponding fuse map for programming. PLD compilers, on the other hand, take higher-level circuit descriptions such as logic schematics, state diagrams, and truth tables as input in addition to Boolean equations. The equation notation and syntax are unique to each particular translator. Some of the translators will perform additional functions such as selecting the appropriate type of PLD for the design, and logic minimization that is intended to reduce the complexity and cost of the device that will ultimately implement the design.

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