Файл: Embedded Controller Hardware Design (Ken Arnold, 2000).pdf

138EMBEDDED CONTROLLER

Hardware Design

We’ll now look at three typical design problems and show how to use the techniques described in this chapter to solve them.

Design Problem 1

For the same three paths in Figure 6-3, find the maximum allowable clock rate, given the slowest EPROM from Table 6-2. Use the specs for the -30 part which has a 300 nS access time and the same address latch specs in Table 6-3. Consider the 8031, EPROM, and 74ALS373 latch specs as discussed in the sections describing Paths A, B and C.

Solution: In this case, we are given the component timing, and we need to solve for the minimum clock period (T = 1/maximum clock frequency).

Path A:

The CPU allows TAVIV = 5*T-100 nS

The EPROM uses Taa = 300 nS

The limiting condition is TAVIV = Taa, so:

5T-100 = 300

5T = 400 T = 80 nS

Path B:

The CPU allows TAVIV = 5*T-100 nS

The EPROM uses Taa = 300 nS

The latch uses TPHL D->Q = 16 nS

The limiting condition is Taa + Tlatch = TAVIV, so:

TAVIV = Taa + Tplatch and TAVIV = 5T-100, so:

5T-100 = 300 + 16

5T = 416 T = 83 nS

Path C:

The limiting condition is TPLIV = Toe of the EPROM, so:

The EPROM Toe from the table is 120 nS

The equation is TPLIV = Toe

140EMBEDDED CONTROLLER

Hardware Design

Solution: In order to determine the required Tce, we need to calculate the memory spec based on the CPU speed. Since /PSEN is connected to the EPROM /CE, the relevant CPU spec is TPLIV. From the 8031 program memory timing table, TPLIV = 3T-100 nS, where T is TCLCL, the clock period. The answer for Tce is in the table for 12 MHz as 150 nS, but it could be computed for an arbitrary clock as:

Tce max = 3*83.3-100 = 150 nS

Taa is different, because the latch delay must be included. In this case the relevant CPU spec is TAVIV, which is 320 nS at 12 MHz. Subtracting the worst case latch delay, Tphl D->Q is 16 nS. Therefore only 320-16 = 304 nS is available to the memory as Taa. The general solution is TAVIV = 5T - 100, so:

Taa = TAVIV-Tplatch = 5*83.3-100-16 = 301 nS

Note that the Taa result is slightly (3nS) different from the value computed using the table. This is not unusual because the specs are not necessarily consistent, nor are they precise to a few nS. Many of the specs are based on statistical estimates of the production population, and are themselves only approximations. Often these specifications are guaranteed but not tested on every device.

Tdf is the time the EPROM takes to turn off its output drivers. This relates to the time the CPU allows for the EPROM to turn off its tri-state driver outputs after /PSEN goes inactive. If this spec is violated there will be bus contention between the CPU and the EPROM for the time of the overlap. The relevant CPU spec is TPHDZ. At 12 MHz, 75 nS are available to the EPROM to disable its outputs. The general form is TPHDZ = T-10 or 73 nS, again slightly different from the table value.

Design Problem 3

For a specific EPROM spec, find the maximum allowable clock rate, given the slowest EPROM from Table 6-2. Use the specs for the -30 part which has a 300 nS access time and the same address latch. Consider the 8051 specs for TPLIV, TAVIV, and TPHDZ.

Solution: In this case, we are given the component timing, and we need to solve for the minimum clock period ( = 1/maximum clock frequency).

141CHAPTER SIX

A Detailed Design Example

The equation for TPLIV = 3T-100 = Tce of the EPROM. The EPROM Tce from the table is 300 nS. Solving for T, we have:

3T - 100 = 300

3T = 400

T = 400/3 = 133 nS.

The EPROM Taa = 300 nS, Taa = TAVIV-Tplatch and TAVIV=5T-100, so:

300 = 5T - 100 - 16

5T = 416 T = 83 nS

The EPROM Tdf = 105 nS, and Tdf = TPHDZ = T-10, so:

105 = T - 10 T = 115 nS

Of all three specs, the longest period is due to the EPROM Tce and TPLIV spec, 1/133 nS = 7.5 MHz. If the /PSEN signal is connected to the -30 EPROM’s /OE pin however, then:

EPROM Toe = 120 nS TPLIV = 3T - 100 = 120 3T = 220

T = 73 nS

With /PSEN connected to /OE the TPLIV spec is not the limit.

The next slowest is due to TPHDZ, resulting in a minimum clock period of 115 nS, corresponding to a maximum clock frequency of 1/115nS = 8.696 MHz.

For the -30 EPROM in Table 6-2, Tdf will be the limiting specification when the access time is fast enough. Tdf is 105 nS, which is greater than the 75 nS available at 12 MHz, resulting in as much as 105 - 75 = 30 nS of bus contention! That is a serious conflict, and should not be allowed to occur.

Note that the access times were well within specifications for 12 MHz operation. If we looked only at the access time specs there is no problem, so the system might appear to work. However, bus contention may occur at the 12 MHz frequency, so the correct answer is 8.7 MHz.

142EMBEDDED CONTROLLER

Hardware Design

If we change the EPROM to the -25 version, it is possible to clock the CPU at its limit of 12 MHz without exceeding any of the other specs. This example shows why it is important to consider ALL the specs, since it is not always the obvious specs that are the limits.

Completing the Analysis

Once the preliminary timing analysis is complete, the next step is to evaluate the noise margin as well as the DC and AC loading for the design. The results of this will determine if any of the signals are incompatible or overloaded, requiring changes to the circuit design or component selection. Of course, any changes made to the design (changing components, adding pull-up resistors, etc.), will require the timing to be re-evaluated. Once again we find that the interactions may cause us to do our design in an iterative fashion. This is part of the reason we don’t want to perform a complete timing analysis from the beginning.

Once the preliminary timing, noise margin, and loading analyses indicate that the design is correct, it is necessary to review all the remaining specifications for all the ICs used in the design. This is not as difficult as it might seem. Most of the hard work is done as part of the preliminary analysis. Also, many of the device specs are simply not applicable to a given design. Examples of these specs include alternative SRAM memory write cycles. A given processor will always use one particular memory write sequence (i.e.: address stable first, then /CS active, then /WE goes low). As a result, the other write cycles and specs can be ignored. Still other specifications are just for information, such as the 8051 TCY spec, which simply informs us that an instruction cycle takes 12 clock cycles on the standard 8051. There will be some other specs that will apply to our design, such as the setup and hold times for some devices. In some cases the specification is a non-constraint, such as the 8051’s TPHDX, input instruction data hold time after /PSEN goes high, specified as 0 nS. A zero hold time indicates that the driving device may remove the instruction at the instant when /PSEN goes inactive. Any device will meet that constraint, since it cannot predict in advance when the /PSEN line will change. Other specs will often have a huge margin as can be seen by inspection. The ’74ALS373 address latch, for instance, requires a minimum enable pulse width that is on the order of 10 nS. The CPU puts out an ALE pulse that is TLHLL = 140 nS wide, so there is obviously lots of margin in that case.

143CHAPTER SIX

A Detailed Design Example

With experience, this iterative design and analysis process becomes much easier, and potential problems are easier to anticipate. However, even with experience it is easy to become lax and leave out the review of the seemingly less important specs. This will often result in a direct application of Ken’s first law of worst-case analysis: “Any specification which is not considered will certainly be violated, causing catastrophic failure at the worst possible time.” That’s usually right before a salary review or in front of an important customer! It is important to review all the specs for the parts to be used in a design. When alternate sources for the devices are to be used, the specifications of these alternates should also be reviewed. Parts from two vendors with the exact same part number may have subtly different specs.

Chapter Six Problems

1)For this problem, use the fastest EPROM program memory from Table 6-2 (the –15 version), the 8031 CPU specs in Table 6-1, and the latch specs from Table 6-3. Ignoring the TCLCL limit on clock speed, how fast can the processor be clocked? Use the connections shown in Figure 6-3, with /PSEN connected to the EPROM /CE pin.

2)Use the same conditions as the problem above, except connect /PSEN to the EPROM /OE control.

3)For a system that has multiple program memories, an address decoder is required in order to generate separate select signals to enable the program memories. What paths and specs will be affected and how will the timing change?

4)For each of the CPU data memory write timing parameters listed in

Table 6-5, list the corresponding SRAM timing parameters from Table 6-6.

This is a blank page.

Programmable

Logic Devices

Application specific integrated circuits (ASIC are ICs that have been designed or programmed to meet the needs of a specific design in which the chips will be used. These are differentiated from standard, or general purpose ICs that may be used in many different applications. General-purpose logic ICs are usually designed “from scratch” using only the most basic circuit elements such as transistors and gates. The cost of building a chip this way can be amortized over a large number of devices if it is used in many different applications.

When an application specific chip is designed from scratch, it is referred to as a full custom logic design. It is the lowest cost to manufacture because it takes the least amount of silicon to implement a given function. Unfortunately the design of a large full custom chip is very expensive (hundreds of thousands to millions of dollars) due to the labor-intensive design and prototyping process, and cannot be justified unless a very large quantity will be manufactured. Originally this was the only way to design chips, but now there are several alternatives for designing ASICs.

Standard cell IC design uses a library of common logic functions that have already been designed and tested. This reduces the amount of design effort in that logic IC blocks such as multiplexers are used in place of the equivalent random logic design implemented with gates. The cells can range in complexity from simple gates to complete CPUs. Standard cell based IC design has become the standard and can now be done even on a PC at a much lower cost than other methods. The cost of manufacturing a minimum production quantity of parts is less (thousands of dollars) than it would be for a full custom design process, but still high enough to be inappropriate for prototyping and low volume production (e.g., less than 5000 units).