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27CHAPTER TWO

Microcontroller Concepts

Up to this point, we have discussed microcontroller architecture in a very general form, as it applies to most common devices. In order to go deeper into the operation of a microcontroller, it is appropriate to present one specific processor as an example. In order to really understand and apply this information to a real hardware and software design, it is necessary to cover one specific machine architecture in detail. That is what we will do in the next section.

The 8051 Family Microcontroller

Processor Architecture

You might wonder why the 8051 family of processors was chosen for this purpose, as it is a relatively old processor. If you read current technical journal articles, you might get the impression that all the action is in 32-bit micros. That is primarily due to the fact that the companies that sell the high-end devices are working very hard to put their newest technology in front of their customers, and they are the ones who write most of the trade articles.

It is important to note that the trade press is always emphasizing the high end 16-bit, 32-bit, and larger processors due to their dependence on the advertising revenue from chip vendors. Though you would never guess it from reading these publications, it is only recently that shipments of 8-bit microcontrollers have exceeded 4-bit units. It will be quite some time before the 16-bit micros will approach the sales volume the 8-bit units have reached, and the 8-bit units are still growing in volume. According to one of the leading industry publications, there are more 8051 derivative CPU chips being produced than any other 8-bit micro. From this point forward, the 8051 family architecture will be used. Later on, other architectures and generic features not implemented in the 8051 will be discussed for completeness. Once you have learned the concepts of the 8051, you will find that the next architecture you need to use will be much easier to learn.

The 8051 microcontroller was chosen as the example processor in this book for several reasons:

•The timing specifications are simple and allow a complete detailed timing analysis within the limited scope of this book.

•Interfacing to the processor’s multiplexed address/data bus provides valuable design experience.

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Hardware Design

•Development tools, including assemblers, simulators and compilers are readily available as freeware shareware and demo versions.

•It is available at a low cost, allowing low cost versions of in-circuit emulators, peripheral components, and single board computers to be purchased by the student.

•The 8051 is the most popular microcontroller family, with many derivatives available, and multiple vendors manufacture it.

•The 8051 architecture is available in a wide range of cost, size, and performance. For example, one version is available in a 20-pin small outline surface mount package for less than a dollar in volume, and another one is about eight to ten times the speed of the original 8051.

•The 8051 CPU is also available as a building block for custom chip designs, and is the most popular CPU for “system on a chip” designs. It is also the only readily available, non-proprietary building block CPU architecture available for chip design.

Software tools for the 8051 family, such as assemblers, compilers and simulators are available at no cost on the internet. Hardware tools, such as the combination software development kit and in-circuit emulator (the SDK which can be used in conjunction with this book), are available for under $100, and complete design documentation is available on the web to allow anyone to build their own.

In addition, the 8051 has the simplest timing specifications of a device which can address external memory, making it practical to go into the details of the design which are necessary to understand. With less than two dozen timing specifications (compared to several times as many for most other equivalent processors), it is possible to cover the timing specifications in detail. Once this process is understood, it is a straightforward jump to understanding and using the larger number of equivalent specifications characteristic of other devices.

Introduction to the 8051 Architecture

This section is intended to provide a broad overview of the 8051 microcontroller architecture. References to “8051” or “’51” in this book generally indicate the entire family of 8051 CPU instruction set compatible devices. Since the original 8051 had an internal read-only memory for programs—which was defined at the time the chips were fabricated—that device is not appropriate

29CHAPTER TWO

Microcontroller Concepts

for our study. For flexibility and simplicity, we will be discussing the 8031, which does not have any internal program memory but instead fetches its program from an external memory device. Otherwise, almost all the versions of the processor family share the same features. If one were to do a practical commercial embedded computer design using an 8051 derivative, one could take advantage of the additional features that are commonly included in the more recent devices. For example, the NMOS versions of this family (e.g. 8031) described here have mostly been displaced by their CMOS counterparts, such as the 80C31. The 8032 and 80C32 with 256 bytes of internal data RAM and an additional timer, at about the same cost, have replaced the ’31 versions. Most of the new versions of these devices have been built upon the features of the ’32 version. Higher speed versions of the device, such as the Dallas Semiconductor 80C320, provide throughput equivalent to almost 100 MHz, compared to the original parts 12 MHz clock. The 8051 CPU element is even available as a standard building block

program and data memory. (An address latch is also required, but not shown in this figure.) The program is

stored in non-volatile ROM memory, such as an EPROM (erasable and programmable read-only memory), and the data is stored in a volatile RAM. In this configuration with external memory, the amount of useable I/O is limited by the number of pins that are used for the address, data, and control lines. Only Port 1 and part of Port 3 is available for user I/O in this case. In its simplest configuration, only the processor’s internal memory is needed for the application, so most of the pins are available for I/O. In that case, the microcontroller is the only required chip, which is also the lowest cost configuration. There are versions of this device that have internal program memory that can be programmed with an inexpensive programmer connected to a PC.

Now that we’ve introduced the 8051 architecture, we need to get into the “low level details” in order to really understand it. Up to this point we’ve had a view from 50,000 feet, where all the landscaping looks perfectly manicured.

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Hardware Design

Now we need to get down to ground level where we can see all the bits of trash and imperfections of reality. Every processor has its own idiosyncrasies, and the 8051 is no exception. While it may seem quite odd at first, it does have some very useful features

pin 1 in the upper left corner.

Figure 2-5 shows the pin numbers, names and functional description of the pin functions for the 8052 CPU in a dual in-line plastic (DIP) package. The 80x1 and 80x2 pin definitions are identical, except for the fact that the 80x1 does not have Timer 2, so those pins are different on the 80x1 parts.

8051 Memory Organization

In order to understand the processor, it is necessary to see how the various memory spaces are organized. The memory organization of the 8051 family of processors may seem complex at first; however, it as not as random as it might seem. There are separate memories for program storage, internal memory and registers, internal I/O functions, and external data memory. The program and external data memories are relatively simple. They each hold up to 64 kilobytes of instructions and data respectively. Program instructions are always fetched from program memory, and are indicated by the CPU activating the /PSEN pin. External data is transferred when the CPU executes a MOVX (MOV eXternal memory) instruction, and the CPU indicates this by activating the /RD or /WR line. The 8051 family chips only have three types of external memory cycles:

•Program read when /PSEN goes low

•External data read when /RD goes low

•External data write when/WR goes low

31CHAPTER TWO

Microcontroller Concepts

This makes interfacing other bus-oriented devices to the processor relatively easy. (Some general purpose or PC CPUs have many different types of bus cycles.)

The internal data address space of the 8051 family is not quite as simple as the external memories. It includes four banks of eight registers, memory that can be accessed one byte or one bit at a time, a stack, and the special function registers (SFRs) which hold the data and control information for the serial port, timers, and other I/O. This internal memory address space can be accessed in several different ways. The internal data space of the CPU can be rather confusing at first, but it is one of the characteristics of the 8051 family, which allows so much to be done with such limited resources.

The 8051 CPU manipulates operands in three memory address spaces:

• 64 kilobyte program memory (external program memory on the 8031) which is enabled when the processor is fetching an instruction to be executed and signaled by activating the CPU’s /PSEN control line. The MOVC instruction also activates /PSEN to enable reading the code memory into the accumulator for accessing lookup tables and other unchanging data stored in the program memory space.

• 64 kilobyte external data memory which is enabled when the processor reads or writes data from the external data memory and signaled by activating the /RD and /WR control lines. This occurs only when a MOVX instruction is used to read or write from external memory.

• Internal data RAM (128 bytes for the ‘31, 256 bytes for the ‘32) and special function registers (SFR). Four register banks (each bank has eight registers), 128 individually addressable memory bits, and the stack all reside in the internal data RAM. The stack depth is limited only by the available internal data RAM. Its location is determined by the 8-bit stack pointer. The 128

byte special