Файл: Embedded Controller Hardware Design (Ken Arnold, 2000).pdf

37CHAPTER TWO

Microcontroller Concepts

•Serial I/O port: The serial I/O port built into the 8031.

•Timer/counters: There are counters that can count external events or count processor clock cycles to operate as timers. Many of the SFRs are also bit addressable.

Bit Addressable Memory

Figure 2-11 shows the organization of bit addressable space in the internal data memory. The bit address space has a total of 256 possible bit addresses. The first 128 bits, 00 to 7F hex, are used to access individual bits of the internal memory from location 20 to 2F hex. The second 128 bits, from 80 to FF hex, allow selected bits in the special function registers to be accessed at the bit level. Not all SFRs are bit addressable, and not all bit addresses are used in

Bit addressable memory allows the manipulation and test of individual bits, which is a very common operation in embedded systems. Almost every application requires that some output bits be used to control an on/off device, such as an indicator or relay. Likewise input bits are used to sense the status of some external device, such as a switch or sensor. The bit addressable address space allows the programmer to operate on information at the bit level just as easily as at the byte level. This is contrasted by most other processors, in which the programmer must write multiple instructions to select the appropriate bit in a byte before processing or testing it.

39CHAPTER TWO

Microcontroller Concepts

Reset Circuitry

The reset input pin should be connected to an external resistor and capacitor, so that the processor will be properly initialized upon initial application of

When power is first applied, capacitor C has zero voltage across it, and reset is held high until the current that flows through R1 charges C. Once the capacitor is charged, the reset pin is at zero volts and inactive. The diode allows the capacitor to discharge when Vcc goes to zero, even for a short period. If there was no diode, and there was a brief power loss, the CPU state would be indeterminate, and would not be reset. Optionally, the processor can be reset by closing switch SW through a series resistor R2, which limits the current through the switch. The current flowing through the switch discharges the capacitor. If resistor R2 was not present, very high currents could flow through the switch. These high currents that flow very briefly while the capacitor is shorted and can cause the switch contacts to fail or even weld the contacts together.

The R1*C time constant must be long enough to guarantee that the processor will be completely reset to a known state upon power up. The delay must allow the oscillator to start up and stabilize, as well as the time it takes the processor to reset after the oscillator is stable. Different processors require different numbers of clock cycles to reset themselves, and the oscillator start-up time can vary widely depending on the frequency reference, voltage, capacitive loads, and other factors. If the processor reset is not long enough, the processor may behave in unpredictable ways, and it may not be apparent that the problem is due to an incomplete reset operation. In most cases, it’s better to have a relatively long reset time constant, on the order of hundreds of milliseconds, to be sure that the processor has been completely reset. External peripherals can also

40EMBEDDED CONTROLLER

Hardware Design

exhibit this problem. During the initial development of the SDK, we experienced occasional problems with the external serial port chip used on the board. The problem turned out to be related to the length of the reset pulse and the period of time after the reset when the chip must be left alone to pull itself together! This sort of problem can be very difficult to trace down, since it is difficult if not impossible to determine when a chip has not been completely reset.

The 8051 is unique in that its reset signal is active high. Other processors use active low reset signals, so the reset circuit must be adjusted to perform the equivalent function with the reset pulse going low at power up and when the capacitor is charged, the reset goes high. The circuit configuration except R and C1 are swapped, as are D1 and the SW/R2 pair.

The circuit in Figure 2-12 is good enough for most applications. However, it is not foolproof. Even with the above precautions, it is possible that the processor state can be jumbled by power transients that are too short to cause a reset. When a processor is used in a critical or long term unattended application, that probably won’t be good enough to meet the need for reliable operation. To deal with this, processor supervisory chips are available to monitor the power supply voltage for out of tolerance fluctuations and automatically reset the processor when the power supply falls out of tolerance. Some of these supervisory chips also have a special “watchdog” timer circuit that expects to be “fed” by a pulse that resets the watchdog counter periodically by a correctly functioning program running on the processor. If the watchdog timer is not “fed” with a pulse periodically, the counter will overflow and it will “bark” by pulling the reset pin active. That way if the processor goes off in the weeds, due to a hardware glitch or a program bug, the CPU will be reset. This is a simple method of obtaining tolerance to fault conditions, but it also requires careful design to avoid undesired reset conditions. It is also the designer’s responsibility to assure that the processor can’t get stuck in a loop while feeding the watchdog timer.

When designing a microcontroller that must operate in high noise environments, or where correct operation is safety critical, special care must be taken to ensure that electromagnetic noise does not cause problems. This noise can come from other parts of the system and environmental conditions such as electromagnetic fields from other devices such as wireless communication devices. With the rapid increase in the number of electronic and wireless devices, this problem is becoming more and more serious. The field of electromagnetic

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Microcontroller Concepts

compatibility (EMC) covers this noise, as well as others such as electrostatic discharge (ESD). A good summary of EMC concepts as they relate to microcontrollers can be found in the Intel application note AP-125, “Designing Microcontroller Systems for Electrically Noisy Environments.”

Oscillator and Timing Circuitry

Timing generation is completely self-contained on the 8051, except for the frequency reference (which can be a crystal or external clock source). The on-board oscillator is a parallel anti-resonant circuit with a frequency range of 1.2 MHz to 12 MHz for the original 8051. There is a divide-by-12 internal clock counter that gives the standard 8051 an instruction cycle of 1 S with a 12 MHz crystal. Higher speed versions of the processor are also available, which use fewer than twelve clocks per instruction cycle. The Dallas 80C320 uses only four clock cycles for most instruction cycles, so it is three times faster than the original CPU using the same clock frequency. The XTAL2 pin is the output of a high-gain amplifier while XTAL1 is its input. A crystal connected between XTAL1 and XTAL2 provides the feedback and phase

The oscillator circuit consists of a crystal connected between the XTAL1 and XTAL 2 pins of the processor, along with two capacitors, one from each XTAL pin to ground to improve stability and start-up characteristics of the oscillator. The internal amplifier and quartz crystal form a series resonant oscillator which operates at the at the crystal’s resonance frequency. The amplifier in the original 8051 was an inverting amplifier, but other variants and other processor families make use of non-inverting amplifiers in some cases. All of the processor’s timing is derived from this oscillator. For the standard 8051 compatible parts,