Файл: Embedded Controller Hardware Design (Ken Arnold, 2001).pdf

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In addition to the memory timing specs shown above, some memories, such as DRAM, have additional constraints as follows:

Cycle times

TRC (read cycle time): how closely read cycles can be spaced

TWC (write cycle time): how closely write cycles can be spaced

Read-modify-write cycle time is a special combined read/write cycle to the same address (e.g. increment a memory location)

DRAM Refresh Cycle

TREF: the maximum time between refresh/read/write cycles before DRAM data loss can occur

One of the DC characteristics of interest in an embedded system is the power consumption, particularly in a battery-operated design. Most static memories have low power or power-down modes activated by disabling the chip select or chip enable line. True CMOS SRAMs have typical power down supply currents in the low or sub-microampere range, allowing their data to be maintained using a battery while the main power is off as in an NVRAM. Some SRAMs are advertised as CMOS, even though they have some NMOS circuits internally to improve speed. These “mixed MOS” designs draw significantly more power and are not usually appropriate for typical battery operated applications.

Practical examples of actual memory specifications used in design of an embedded system can be found in Chapter Six.

Asynchronous vs. Synchronous Memory

An asynchronous memory is one that does not require any clock signals and delivers its output with a delay of one access time (the internal memory logic propagation time) after the address and control lines stabilize. Most SRAMs, like the SRAM described above, are asynchronous, but a few are synchronous and have clocks for internal latches to store the address and write enable signals. DRAMs are synchronous because they require RAS and CAS strobes to load the internal data latches. Generally asynchronous parts are easier to design with because of simpler timing constraints and direct compatibility with most processor buses.

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Error Detection and Correction

Error detection circuitry stops an operation before erroneous data is used, such as a parity error trap. Error correction on the other hand, uses redundant data to reconstruct the original data to be used when operation must continue with­ out interruption. Error detection and correction are not often used in small systems because of the relatively low probability of error and high cost of error detection and correction hardware. In systems like PCs and workstations, larger RAM memories result in the need for error detection as a minimum, and error correction in systems requiring high reliability. In most PCs, a ninth bit in each byte stores parity information, and if there is a parity error, an interrupt trap will stop operation and display an error message.

There are two types of errors: hard errors and soft errors. If an error occurs only once, due to noise or a transient error condition, it is referred to as a soft error. A hard error is one that always occurs, such as a read/write memory bit that is stuck in one state and can’t be changed.

Error Sources

Hard errors are usually caused by a permanent hardware defect, while soft errors can be caused by any one of several events, including timing errors, synchronization problems, software bugs, or even the passage of a charged subatomic particle resulting from the decay of trace radioactive materials flying through an IC. As a designer of an embedded system, it is necessary to allow for the occurrence of these events, and minimize the severity of their effect on the overall system. In order to accomplish that goal, it is necessary to detect the occurrence of such an event as a minimum.

Confidence Checks

The confidence check is frequently used to detect these errors, and can be modified to correct certain subsets of the errors as well. Probably the most well known of the detection techniques is parity. Its widespread use is due to the simplicity of its implementation. In the most common form, a single bit is added to every word, containing the parity check bit. The parity bit is set or cleared depending on whether there are an even or odd number of ones in the

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original word to be checked. Whenever the data is handled, the contents are checked against the parity bit. If any one bit in the word has changed, then the parity of the data will not match the parity bit accompanying the data, indicating an error. For a single byte or word, this is usually a reasonable assumption, however for a large block of data, it is not reasonable. Horizontal parity refers to the parity of a single word of data, while vertical parity refers to the parity of one bit position in multiple words. They are combined to form block parity, which assigns one parity bit for each word horizontally and one parity bit for each bit position in the block of words.

Block parity allows the detection and correction of single bit errors. Since a single bit will cause one horizontal and one vertical parity error to occur, correcting the bit in error requires only complementing the bit belonging to the row and column corresponding to the parity errors. Note that multiple errors may not be corrected or even detected, depending on where they occur.

Here is an example using odd parity:

1 0 1 1 p=0 odd horizontal parity

1 1 1 1 p=1 even horizontal parity +1 = odd parity 1 0 0 1 p=1 even horizontal parity +1 = odd parity 1 0 1 1 p=0 odd horizontal parity

1 0 0 1 < The odd vertical parity bits for the four words above

Another version of parity checking is called Hamming code after its inventor, R.W. Hamming. It is a code in which multiple parity bits are appended to each word in such a way that a single bit error will generate a group of parity bits having a value equal to the data bit number in error.

A checksum is another technique that can be used to detect an error in a group of characters. The idea is simple enough: sum all the data words and keep the least significant bits of the sum. (For you math majors, that’s sum­ ming the data modulo 2n, for n bit words.) Checksums are frequently used by various types of memory and logic device programmers to verify that the desired program has been “burned” into the device. A checksum will detect some, but not all, of the common errors in a block of data. For example, it won’t detect errors due to the data being stored in the wrong sequence, since the sum of the numbers is the same regardless of the order. A practical

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example is when a 16-bit CPU’s program is burned into two 8-bit memories, one containing the lower byte and one containing upper byte of the instructions. When the bytes in the block of memory are summed, the answer is the same, even if the two devices are swapped! Thus, a serious and common error would not be discovered.

The CRC (cyclic redundancy code) is used to detect changes within a block of data or its order. The CRC is based on a polynomial that is calculated using shifts and XOR (exclusive OR) logic to generate a number that is dependent on the data and the order of the data. The detailed operation of a CRC is beyond the scope of this book, but is based on the same polynomials used for generating pseudo-random numbers. It is commonly used for checking blocks of data on magnetic storage devices and communication links.

Memory Management

In order to understand what memory management is, it’s helpful to understand the motivation behind its use. There are two kinds of memory management: memory address relocation and memory performance enhancement. They are often used in conjunction, as is commonly done in personal computers. This section covers the performance enhancement aspects, while the address relocation issues will be covered in Chapter Six.

The differences between different storage technologies, in terms of performance and cost, vary over many orders of magnitude. For example, semiconductor memory devices have access times that are many orders of magnitude faster (nanosecond vs. millisecond access time) than that of magnetic disks. Of course, magnetic disks also have a cost several orders of magnitude less than semiconductor memory on a cost per bit basis. This disparity in price and performance has lead to the idea of using small, fast memories to store the most frequently accessed subset of the complete collection of data present

in a larger, slower memory. This technique of buffering, often referred to as caching memory contents in a fast memory, is essentially similar whether it is applied to the memory attached to a CPU or the magnetic or optical storage mechanisms. In fact, there may be several layers of caching in a given system, starting with the smallest, fastest memory closest to the CPU, followed by slower but larger memories.

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Memory price is inversely proportional to speed, as indicated below:

Cache Memory

When a high speed memory is used to provide rapid access to the CPU for most frequently used portion of main memory, it is referred to as a CPU cache memory. Likewise, when the main memory is used to provide rapid access to data stored on a disk, it is referred to as a disk cache.

The objective of these approaches is to maximize the likelihood that most pieces of data will be found in the small and fast memory most of the time, thus reducing the average effective access time. The object is to succeed at finding most data in the small fast memory most of the time, minimizing the number of accesses to the big slow memory. Fast SRAM is used as a fast temporary buffer (memory cache) between main memory and the CPU. Main memory DRAM is used to buffer disk data (disk cache). Most hard disk drives also have some internal fast semiconductor RAM to cache data as it is being transferred to and from the disk.

Virtual Memory

Disk storage can be used to emulate a larger primary memory than is actually available. Demand paged virtual memory provides an apparently large primary memory by swapping pages of data between real primary memory and disk.

This is a combination of hardware for translating logical (virtual) addresses, moving pages as needed, and operating system software to determine where and when pages should be kept and detect access attempts to pages which are not in primary memory.

When address relocation mechanisms are combined with disk caching and