Файл: Embedded Controller Hardware Design (Ken Arnold, 2001).pdf

131CHAPTER SIX

A Detailed Design Example

the output (Q) is only 23 nS, much less than the time the CPU takes to put its address out on the bus. The delay in the ALE path is:

TLHLL-TAVLL = 140 - 60 = 80 nS

Since the latch is enabled in 23 nS, but the address is not available from the CPU until 57 nS later, this path is not considered. In this, as in most designs, the ALE delay path is not critical, so it is ignored. This must be considered for some CPUs, such as the Dallas Semiconductor high-speed 80C320 family of microcontrollers. Path B, from D to Q, is always worth examining.

Path B

From the time a valid address is available on port 0 (the multiplexed bus), plus the maximum D to Q delay through the latch, and the EPROM address access time, until valid data is on the bus.

The CPU allows the same total of 320 nS delay time for this path as above. In this case however, there is the additional delay of the latch that reduces the time available to the memory. The latch is specified for a maximum D to Q delay, tP D->Q of 16nS worst case. So from the 320 nS available, 16 nS is used by the latch, and 300 nS is used by the EPROM, leaving only four nanoseconds of margin!

TAVIV - EPROM tACC - Latch tP D->Q = 320 - 300 - 16 = 4 nS margin

This is a slim, but acceptable margin, as long as the device outputs can drive the actual loads on their outputs. If the load capacitance exceeded the speci­ fied test load capacitance usually listed in the notes in the timing section, then the rise/fall time would be extended, possibly throwing this design out of the specified limits at the full 12 MHz clock speed.

Path C

For Path C, we need to evaluate the delay between the time the CPU enables the program memory and when the memory instruction output appears on the bus. The enable access time is from the activation of /PSEN, which enables the EPROM chip enable (/CE), until the EPROM provides a stable and valid instruction on the data bus.

132EMBEDDED CONTROLLER

Hardware Design

Once again, the design margin is the time allowed by the CPU, less the time taken by the external circuits. The CPU allows TPLIV or 150 nS.

TPLIV - EPROM tCE = 150 - 300 = -150 nS NEGATIVE design margin!

When /PSEN is directly connected to the EPROM /CE line, the CPU provides 150 nS (TPLIV) for the EPROM enable access time, but the -30 EPROM tCE is 300 nS, which is 150 nS TOO SLOW!

At this point, we have several options:

•Decrease the CPU clock speed.

•Buy a faster EPROM.

•Change the wiring: connect /PSEN to /OE instead of /CE.

Let’s examine these three alternatives more closely.

1)Reduce the clock speed of the CPU to conform to the EPROM’s chip enable access time. This has the obvious disadvantage that the processor will run more slowly.

2)Buy an EPROM with faster chip enable access time. Faster parts cost more and, in this case, the fastest device in the table has a chip enable access time of 170 nS, which is still too slow.

3)Rewire the /PSEN line to EPROM output enable input (/OE) and connect the chip enable (/CE) to ground. This does not require slowing the chip or using a faster, more expensive memory.

There is one other solution that is not available on the standard 8051 processor: the use of “wait states” which stretch the memory cycle timing by one or more clock cycles. The standard 8051 family parts do not incorporate this feature, but the high-speed versions do. The 80C320 family of high-speed microcon­ trollers from Dallas Semiconductor does allow wait states. These devices have internal registers that can be programmed to stretch memory cycles as needed to accommodate slower memories. Some other types of processors require external hardware to insert wait states.

Comparing all options, the simplest solution is probably 3). Let’s see what happens to the Path C timing design margin calculation when we use that approach. In this version, the CPU’s /PSEN line drives the EPROM’s /OE input, with the /CE grounded. As before, the CPU allows TPLIV or 150 nS,

133CHAPTER SIX

A Detailed Design Example

but in this case we use the EPROM’s output enable access time, tOE. Looking back at the EPROM specifications, we find that for the slowest (-30) part, the worst-case value for tOE is 120 nS.

TPLIV - EPROM tOE = 150 - 120 = +30 nS design margin

When /PSEN is directly connected to the EPROM /OE line, the CPU provides 150 nS (TPLIV) for the EPROM enable access time, and the -30 EPROM tOE is 120 nS, which is more than fast enough. This design change allows the CPU to run at the full 12MHz rating. The example shows how we may have to change the design in order to optimize the timing, and the iterative nature of the design process.

As in everything else, there are some drawbacks and implications for this approach that need to be considered:

•The EPROM is always enabled when the /CE input is grounded, so only one EPROM can be used this way. This has the disadvantage that the EPROM draws its maximum operating power constantly.

•Use of /CE to enable the device reduces power consumption, which is important for battery powered applications, especially when there are multiple devices. Enabling with the /CE input allows for the use of mul­ tiple memory chips in the system by using a memory address decoder to decode the appropriate address range. The decoder output can drive the selected memory device /CE input lines one at a time, just as we saw in the previous module on memory address decoding. That way only one of the memory devices is powered at a given time. The memories’ /OE lines would be connected to the processor’s /PSEN signal output, so that slower memories could still be used. As is the case for other specs, the speed or power consumption of the system can be optimized.

This concludes our example, but it is evident that there are many other timing specifications that must be evaluated for a given design. Fortunately, the same methods we have used here are applicable to the other timing specifications and devices used in a typical embedded controller system. This completes the preliminary evaluation of the program fetch cycle memory access times, which are often among the most difficult to meet. The next step is to analyze the data memory cycle timing.

135CHAPTER SIX

A Detailed Design Example

reads from the SRAM while Figure 6-7 shows the SRAM read cycle timing diagram. Table 6-4 gives the data memory timing parameters for the 8031, and Table 6-5 lists the SRAM’s ready cycle timing parameters. The CPU’s TAVDV spec places an upper limit on the data memory’s access time, tAA, for path A.

Figure 6-7: SRAM read cycle timing diagram.

Table 6-5: SRAM read cycle timing parameters.

A)The delay from when the CPU provides a valid address A8..15 on Port 2 until the end of the SRAM address access time, resulting in valid data from the SRAM on the data bus. The CPU requires that the data from the SRAM be available 600 nS (TAVDV) after being presented with a valid