Файл: Embedded Controller Hardware Design (Ken Arnold, 2001).pdf

218EMBEDDED CONTROLLER

Hardware Design

Since many systems employ logic using different power supply voltages, such as mixed 5 and 3.3 volt logic, it is important to verify that the signals that cross the boundary have sufficient noise margins, and do not exceed the maximum input voltage ratings. In some cases, level conversion or voltage clamping circuits may be necessary. Some 3 volt logic devices are tolerant of 5 volt signal levels on some of their input pins, simplifying the design. On the other hand, 3 volt CMOS outputs can often drive 5 volt logic with TTL compatible inputs directly.

3. Check DC Fan-Out: Output Current Drive vs. Loading

Maximum logic output currents (IOL and IOH) are specified, usually at a specific output voltage (VOL and VOH respectively) . The total load current that an output drives must be compared to the inputs and any resistors the output must drive, and sufficient margin must be allowed to guarantee proper operation.

Some logic outputs, such as IRQ and DMA request lines, frequently use opendrain or open-collector buses, which require pull-up resistors. Open-drain or open-collector outputs must be identified and pulled up with an appropriate resistor. Unused inputs should be pulled to their inactive state: either pulled up to the supply through a resistor, or connected to ground, as appropriate.

Pull-up resistor values must be chosen to minimize the rise time using as small a value as will satisfy the maximum IOL of the weakest open-drain device driving the line.

4. AC (Capacitive) Output Drive vs. Capacitive Load and De-rating

Device timing is usually specified under specific loading conditions on the outputs. If the actual capacitive load on the outputs, consisting of the driven logic inputs and stray wiring capacitance, exceeds the load capacitor specified in the output device’s timing test conditions, then the timing specs will not be valid. If the amount of overload is not severe, it is possible to estimate the additional delay required to charge the excess capacitance. The delay depends upon the available charging current and actual load capacitance.

219APPENDIX A

Hardware Design Checklist

DC and AC loading can be summarized in a spreadsheet as shown below:

5. Verify Worst Case Timing Conditions

All timing specifications should be evaluated for potential timing violations, as covered in chapter 6. This is particularly important for signals that are heavily loaded requiring de-rating of the timing specs, or tri-state signals that are subject to bus contention problems.

6. Determine if Transmission Line Termination is Required

The signal rise time and maximum trace length must be evaluated to deter­ mine if a signal interconnect must be treated as a transmission line, requiring constant impedance along the length of the trace, and termination to prevent reflections. If the signal has a fast rise time and trace length, L, greater than about one-sixth the edge length of the pulse, then it is necessary to analyze the circuit as a transmission line using this formula:

L = Tr / D where

L = length of rising or falling edge in inches (in)

Tr = rise time in picoseconds (pS)

D = delay in picoseconds per inch (pS/in)

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Hardware Design

For traces on a standard printed circuit board, the value for D will be in the range of 100 to 200 pS/in. Depending upon how much distortion you’re willing to live with, the critical trace length will be between one-sixth and one-quarter of the length of a trace corresponding to the signal’s transition. For a trace that is shorter than one-sixth the length of the signal’s rising or falling edge, the circuit seldom needs to be considered to be a transmission line. Traces that are much longer than one-quarter the length of the fastest edge will start to behave as transmission lines, exhibiting reflections of the signal when the transition gets to the far end of the trace and is reflected back to the near end. Once the trace is about half of the length it takes for a logic transition to propagate, the problems become quite pronounced.

7. Clock Distribution

Distribution of clock signals must be done in a way that compromises the need to minimize clock skew, while avoiding reflections that can cause unac­ ceptable clock transitions due to transmission line effects. Distributing clocks in such a way as to avoid excessive skew implies the use of a clock tree to provide equal time delay to each load. However, a tree topology is in direct conflict with the need to maintain a single, stubless transmission line. The ideal transmission line is essentially “daisy-chained” with a trace that has constant impedance across its length and has no stubs, but that usually results in maxi­ mum timing skew! Clock signals should also be isolated from other signals to prevent crosstalk between the clock and other signals. Clock signals should generally NOT be gated, to avoid undesirable side effects.

8. Power and Ground Distribution

Ground and power planes are recommended on printed circuits wherever possible, because they allow low impedance connections and provide high frequency decoupling from inter-plane capacitance. Ground connections should be as short as possible, especially for ground pins on multiple output logic devices, to prevent ground bounce.

221APPENDIX A

Hardware Design Checklist

Capacitors for Bypassing Power Supply Noise

The power and ground pins of every IC should be bypassed using a capacitor with low impedance at the frequencies of interest (determined by rise time, not clock rate). The self-resonance of larger capacitors, such as 0.1 microfarad, may result in little effect on the fast current transients present in high-speed logic chips. 0.01 or 0.001microfarad (or even hundreds of picofarads) low inductance capacitors, are more appropriate for fast logic devices having sub-5 nanon­ second rise times. Multi-layer ceramic dielectric surface mount capacitors work better than leaded, tantalum or electrolytic capacitors at high frequencies. Each board in a system should also have a larger tantalum or electrolytic capacitor to provide medium frequency bypassing for peak currents.

When possible, power supply and ground connections should be made independently to the power supply, to minimize common impedances, also known as ground loops. This is especially important for circuits containing mixed analog and digital circuitry.

Mixed Analog and Digital Circuitry

The analog power supply should be separately regulated from the digital supply, to provide a quiet power source to the analog circuitry. Separate power and ground planes should be maintained to minimize coupling between noisy digital circuits and sensitive analog or RF (radio frequency) circuits. Analog power planes should not overlap with digital planes, as the digital noise will couple through the inter-plane capacitance. Digital and analog grounds should only be interconnected at one point, usually very near the analogdigital conversion IC.

High impedance analog signals should be physically and electrically isolated from digital signals to minimize digital noise on the analog signals.

Digital inputs that are driven by analog circuitry should be clamped, using a series resistor and low forward voltage Schottky diodes, to power and ground to clamp the signals to levels that are within the logic input specification levels.

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Hardware Design

Safety

High voltage conductors should be physically and electrically isolated from low level and user accessible signals to avoid potential shock hazards. All conductors should be sized large enough to allow carrying maximum current, under short circuit conditions, and protective devices, such as fuses and PTC switches, should be used to prevent. Conductors carrying more than 40 volts and telephone line conductors must be isolated by at least onequarter inch from other conductors or transformer isolated for safety agency and telecom approvals.

9. Asynchronous Inputs

Asynchronous inputs should be synchronized using two levels of flip-flops to minimize the probability of a metastable state when asynchronous inputs are sampled. This is particularly important for programmable logic devices, which may have slow recovery times from metastable states.

10. Guarantee Power-On Reset State

Verify that any devices, such as CPU, PLDs, and registers, are reset to a known state when power is applied, or whenever power falls below normal operating levels (brown out condition). All CPUs, counters, registers, shift registers and memory devices are subject to unpredictable behavior when the power is out of spec and must be reset after the power returns to specified levels.

11. Programmable Logic Devices

Verify that all flip-flops in the device will be in a known state upon power-up, and that any counters and state machines with unused states will transition to a valid state in the event that they get into an invalid state.

Leave a few available input and output pins available to facilitate changes in the event that additional logic functions become necessary.

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Hardware Design Checklist

12. Deactivate Interrupt and Other Requests on Power-Up

Interrupt, DMA, and other edge sensitive input requests should be disabled upon power up to minimize the chance that a spurious event will be pro­ cessed when the system is turned on.

13. Electromagnetic Compatibility Issues

Signals that enter and leave the printed circuit boards should be filtered to reduce the unintentional emission of radio frequencies as much as possible. Digital circuits should also be packaged in conductive enclosures when pos­ sible to minimize the digital signals from being radiated as electromagnetic interference to other devices, and to protect the device from external electro­ magnetic fields and static discharge.

High order harmonics from clock edges can be mitigated by the use of ferrite beads (small value inductors) that reduce the amplitude of the higher clock harmonics. Clocks should also be kept away from I/O signals and connectors to reduce the coupling of clock noise to wires and interconnects that can act as antennas, conducting and radiating clock harmonics as radio interference.

14. Manufacturing and Test Issues

Manufacturing of boards can be made simpler if the design implements a method that allows programming processors, memories, and PLDs while the components are mounted to the card. This facilitates manufacturing the boards prior to pro­ gramming the devices. This also facilitates loading test programs into the board to allow more effective tests to determine of the board is operating as intended.

Signals which control or enable outputs or programming signals that might need to be disabled and driven externally for test purposes should be isolated from a test point with a series resistor, allowing an external test or programming circuit to drive the signal without damaging the output device on the board.

The inclusion of easily probed test points also makes it easier to diagnose failures by making it easier to probe critical signals on the board.

References, Web Links,

and Other Sources

Since he number of information sources that may be of interest is too great to include a comprehensive list—and many links to the information become obsolete—the sources noted in this chapter are just the starting points for more detailed information. Some of the books listed here relate directly to this subject, and others are some of my personal favorites, as they contain information which I make reference to regularly.

An important thing to keep in mind for any source of information is who the source is and how they derive their income. Trade magazines are useful, and because they are free to qualified subscribers, they are very popular source of information. Unfortunately, they derive their income solely from their adver­ tisers, and most of the articles are written by advertisers and the magazine editors. As a result, they often portray a very biased view of what’s going on in the industry. Likewise, web sites and other advertiser supported information sources often have very slanted versions of reality. There are a few exceptions, such as magazines that are supported by subscriptions as well as advertising, that have articles written by those of us who are down in the trenches. They often provide a more accurate, though still biased, view of what’s really going on.

Books

The Art of Electronics, by Horowitz and Hill, also the accompanying Student Manual, by Hayes and Horowitz, to accompany the text. This is an all-time favorite tome that covers an incredibly wide range of topics in a very readable and useful way. The student guide provides a refreshing review of the practical side of electronics, and will be invaluable for those who need to learn more about electronics.